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11	Performance enhancement techniques for low power digital phase locked loops Elshazly, Amr 16 July 2014 (has links) Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014 Phase locked loops Delay locked loops Supply noise mitigation background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Integrated circuits Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise -- Prevention Low voltage systems Frequency synthesizers
12	Modélisation à haut niveau de systèmes hétérogènes, interfaçage analogique /numérique / High level modeling of heterogeneous systems, analog/digital interfacing. Cenni, Fabio 06 April 2012 (has links) L’objet de la thèse est la modélisation de systèmes hétérogènes intégrant différents domaines de la physique et à signaux mixtes, numériques et analogiques (AMS). Une étude approfondie de différentes techniques d’extraction et de calibration de modèles comportementaux de composants analogiques à différents niveaux d’abstraction et de précision est présentée. Cette étude a mis en lumière trois approches principales qui ont été validées par la modélisation de plusieurs applications issues de divers domaines: un amplificateur faible bruit (LNA), un capteur chimique basé sur des ondes acoustiques de surface (SAW), le développement à plusieurs niveaux d’abstraction d’un capteur CMOS vidéo, et son intégration dans une plateforme industrielle. Les outils développés sont basés sur les extensions AMS du standard IEEE 1666 SystemC mais les techniques proposées sont facilement transposables à d’autres langages tels que VHDL-AMS ou Verilog-AMS utilisés en conception de dispositifs mixtes. / The thesis objective is the modeling of heterogeneous systems. Such systems integrate different physical domains (mechanical, chemical, optical or magnetic) therefore integrate analog and mixed- signal (AMS) parts. The aim is to provide a methodology based on high-level modeling for assisting both the design and the verification of AMS systems. A study on different techniques for extracting behavioral models of analog devices at different abstraction levels and computational weights is presented. Three approaches are identified and regrouped in three techniques. These techniques have been validated through the virtual prototyping of different applications issued from different domains: a low noise amplifier (LNA), a surface acoustic wave-based (SAW) chemical sensor, a CMOS video sensor with models developed at different abstraction levels and their integration within an industrial platform. The flows developed are based on the AMS extensions of the SystemC (IEEE 1666) standard but the methodologies can be implemented using other Analog Hardware Description Languages (VHDL-AMS, Verilog-AMS) typically used for mixed-signal microelectronics design. Flot Modélisation comportementale Modèle de représentation d'état Modèle d'ordre réduit Modèle de calcul (MoC) OSCI SystemC AMS VHDL-AMS Capteur d'image Modèle transactionnel (SystemC TLM) Behavioral Modeling AMS IP reuse State Space Model Reduced Order Modeling Model of Computation (MoC) OSCI SystemC AMS VHDL-AMS System Identification Image Sensor

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Performance enhancement techniques for low power digital phase locked loops

Modélisation à haut niveau de systèmes hétérogènes, interfaçage analogique /numérique / High level modeling of heterogeneous systems, analog/digital interfacing.