Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

With the development of VLSI and wireless communication technology, portable devices such as personal digital assistants (PDAs), pocket PCs, and mobile phones have gained a lot of popularity. Many such devices incorporate a speech recognition engine, enabling users to interact with the devices using voice-driven commands and text-to-speech synthesis. The power consumption of DSP microprocessors has been consistently decreasing by half about every 18 months, following Gene's law. The capacity of signal processing, however, is still significantly constrained by the limited power budget of these portable devices. In addition, analog-to-digital (A/D) converters can also limit the signal processing of portable devices. Many systems require very high-resolution and high-performance A/D converters, which often consume a large fraction of the limited power budget of portable devices. The proposed research develops a low-power audio signal enhancement system that combines programmable analog signal processing and traditional digital signal processing. By utilizing analog signal processing based on floating-gate transistor technology, the power consumption of the overall system as well as the complexity of the A/D converters can be reduced significantly. The system can be used as a front end of portable devices in which enhancement of audio signal quality plays a critical role in automatic speech recognition systems on portable devices. The proposed system performs background audio noise suppression in a continuous-time domain using analog computing elements and acoustic echo cancellation in a discrete-time domain using an FPGA.

CNPq;CAPES / Neste trabalho é investigado o uso de codificação analógica conjunta fonte-canal em uma rede de sensores sem fio onde a fonte de informação é alimentada pelo destino por meio de transmissões de rádio frequência. É assumido que o destino não possui restrições energéticas. Logo após coletar energia do destino, a fonte transmite sua informação utilizando a energia recebida. As fases de transferência de energia e de transmissão de informação são multiplexadas no tempo. Como uma fração do intervalo de transmissão é utilizado para transferência de energia, as amostras da fonte são armazenadas e comprimidas utilizando tanto códigos analógicos paramétricos quanto não paramétricos com compressão de dimensão (ou largura de banda) N:K para transmiti-las utilizando a fração do intervalo restante. São analisados tanto esquemas com largura de banda casadas e não casadas entre fonte e canal. Além disso, é investigado também o parâmetro de compartilhamento de tempo ótimo o qual otimiza o desempenho da transmissão analógica. Por fim, é demonstrado que os esquemas analógicos propostos podem superar um sistema digital em termos de relação sinal-distorção. / We investigate the use of discrete-time analog joint source channel coding (JSCC) in a wireless sensor network (WSN) where the source of information is wirelessly powered by the destination, which does not have energy constraints. Right after harvesting energy from the destination, the source transmits its information using the energy harvested. Wireless energy transfer and information transmission are multiplexed via a time-switching protocol. As a fraction of the time slot is spent for energy transfer, the source samples are saved and compressed using either parametric or non-parametric N:K dimension compression analog JSCC to transmit the information in the remaining fraction of the time slot. We analyze both matched and unmatched source and channel bandwidths. Moreover, we investigate the time-sharing parameter that optimizes the analog system performance and show that the proposed analog scheme can outperform a fully digital system.

CNPq;CAPES / Neste trabalho é investigado o uso de codificação analógica conjunta fonte-canal em uma rede de sensores sem fio onde a fonte de informação é alimentada pelo destino por meio de transmissões de rádio frequência. É assumido que o destino não possui restrições energéticas. Logo após coletar energia do destino, a fonte transmite sua informação utilizando a energia recebida. As fases de transferência de energia e de transmissão de informação são multiplexadas no tempo. Como uma fração do intervalo de transmissão é utilizado para transferência de energia, as amostras da fonte são armazenadas e comprimidas utilizando tanto códigos analógicos paramétricos quanto não paramétricos com compressão de dimensão (ou largura de banda) N:K para transmiti-las utilizando a fração do intervalo restante. São analisados tanto esquemas com largura de banda casadas e não casadas entre fonte e canal. Além disso, é investigado também o parâmetro de compartilhamento de tempo ótimo o qual otimiza o desempenho da transmissão analógica. Por fim, é demonstrado que os esquemas analógicos propostos podem superar um sistema digital em termos de relação sinal-distorção. / We investigate the use of discrete-time analog joint source channel coding (JSCC) in a wireless sensor network (WSN) where the source of information is wirelessly powered by the destination, which does not have energy constraints. Right after harvesting energy from the destination, the source transmits its information using the energy harvested. Wireless energy transfer and information transmission are multiplexed via a time-switching protocol. As a fraction of the time slot is spent for energy transfer, the source samples are saved and compressed using either parametric or non-parametric N:K dimension compression analog JSCC to transmit the information in the remaining fraction of the time slot. We analyze both matched and unmatched source and channel bandwidths. Moreover, we investigate the time-sharing parameter that optimizes the analog system performance and show that the proposed analog scheme can outperform a fully digital system.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009 / Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento. / Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Indiana University-Purdue University Indianapolis (IUPUI) / The recording and processing of bioelectric signals over the decades has led to the development of many different types of analog filtering and amplification techniques. Meanwhile, there have also been many advancements in the realm of digital signal processing that allow for more powerful analysis of these collected signals. The issues with present acquisition schemes are that (1) they introduce irreversible distortion to the signals and may ultimately hinder analyses that rely on the unique morphological differences between bioelectric signal events and (2) they do not allow the collection of frequencies in the signal from direct-current (DC) to high-frequencies. The project put forth aims to overcome these two issues and present a new scheme for bioelectric signal acquisition and processing. In this thesis, a system has been developed, verified, and validated with experimental data to demonstrate the ability to build an invertible universal amplifier and digital restoration scheme. The thesis is primarily divided into four sections which focus on (1) the introduction and background information, (2) theory and development, (3) verification implementation and testing, and (4) validation implementation and testing. The introduction and background provides pertinent information regarding bioelectric signals and recording practices for bioelectric signals. It also begins to address some of the issues with the classical and present methods for data acquisition and make the case for why an invertible universal amplifier would be better. The universal amplifier transfer function and architecture are discussed and presented along with the development and optimization of the characterization and the inversion, or restoration, filter process. The developed universal amplifier, referred to as the invertible universal amplifier (IUA), while the universal amplifier and the digital restoration scheme together are referred to as the IUA system. The IUA system is then verified on the bench using typical square, sine, and triangle waveforms with varying offsets and the results are presented and discussed. The validation is done with in-vivo experiments showing that the IUA system may be used to acquire and process bioelectric signals with percent error less than to 6% when post-processed using estimated characteristics of and when compared to a standard flat bandwidth high-pass cutoff amplifier.