Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 97-99). Also available in electronic format on the Internet.

Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however. have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy. just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time. This dissertation discusses power/energy optimization and performs analysis on both synchronous and asynchronous logic. The major contributions of this dissertation include: 1 ) A 2-Dimensional Pipeline Gating technique for synchronous pipelined circuits to improve their power awareness has been proposed. This technique gates the corresponding clock lines connected to registers in both vertical direction (the data flow direction) and horizontal direction (registers within each pipeline stage) based on current input precision. 2) Two energy reduction techniques, Signal Bypassing & Insertion and Zero Insertion. have been developed for NCL circuits. Both techniques use Nulls to replace redundant Data 0's based on current input precision in order to reduce the switching activity while Signal Bypassing & Insertion is for non-pipelined NCI, circuits and Zero Insertion is for pipelined counterparts. A dynamic active-bit detection scheme is also developed as an expansion. 3) Two energy estimation techniques, Equivalent Inverter Modeling based on Input Mapping in transistor-level and Switching Activity Modeling in gate-level, have been proposed. The former one is for CMOS gates with feedbacks and the latter one is for NCL circuits.

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Lee Chi-wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 191-196). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.i / 摘要 --- p.iii / Acknowledgements --- p.v / Table of Contents --- p.vii / List of Tables --- p.x / List of Figures --- p.xi / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Synchronous Design --- p.1 / Chapter 1.2 --- Asynchronous Design --- p.2 / Chapter 1.3 --- Discrete Cosine Transform --- p.4 / Chapter 1.4 --- Motivation --- p.5 / Chapter 1.5 --- Organization of the Thesis --- p.6 / Chapter Chapter2 --- Asynchronous Design Methodology --- p.7 / Chapter 2.1 --- Overview --- p.7 / Chapter 2.2 --- Background --- p.8 / Chapter 2.3 --- Past Designs --- p.10 / Chapter 2.4 --- Micropipeline --- p.12 / Chapter 2.5 --- New Asynchronous Architecture --- p.15 / Chapter Chapter3 --- DCT/IDCT Processor Design Methodology --- p.24 / Chapter 3.1 --- Overview --- p.24 / Chapter 3.2 --- Hardware Architecture --- p.25 / Chapter 3.3 --- DCT Algorithm --- p.26 / Chapter 3.4 --- Used Architecture and DCT Algorithm --- p.30 / Chapter 3.4.1 --- Implementation on Programmable DSP Processor --- p.31 / Chapter 3.4.2 --- Implementation on Dedicated Processor --- p.33 / Chapter Chapter4 --- New Techniques for Operating Dynamic Logic in Low Frequency --- p.36 / Chapter 4.1 --- Overview --- p.36 / Chapter 4.2 --- Background --- p.37 / Chapter 4.3 --- Traditional Technique --- p.39 / Chapter 4.4 --- New Technique - Refresh Control Circuit --- p.40 / Chapter 4.4.1 --- Principle --- p.41 / Chapter 4.4.2 --- Voltage Sensor --- p.42 / Chapter 4.4.3 --- Ring Oscillator --- p.43 / Chapter 4.4.4 --- "Counter, Latch and Comparator" --- p.46 / Chapter 4.4.5 --- Recalibrate Circuit --- p.47 / Chapter 4.4.6 --- Operation Monitoring Circuit --- p.48 / Chapter 4.4.7 --- Overall Circuit --- p.48 / Chapter Chapter5 --- DCT Implementation on Programmable DSP Processor --- p.51 / Chapter 5.1 --- Overview --- p.51 / Chapter 5.2 --- Processor Architecture --- p.52 / Chapter 5.2.1 --- Arithmetic Unit --- p.53 / Chapter 5.2.2 --- Switching Network --- p.56 / Chapter 5.2.3 --- FIFO Memory --- p.59 / Chapter 5.2.4 --- Instruction Memory --- p.60 / Chapter 5.3 --- Programming --- p.62 / Chapter 5.4 --- DCT Implementation --- p.63 / Chapter Chapter6 --- DCT Implementation on Dedicated DCT Processor --- p.66 / Chapter 6.1 --- Overview --- p.66 / Chapter 6.2 --- DCT Chip Architecture --- p.67 / Chapter 6.2.1 --- ID DCT Core --- p.68 / Chapter 6.2.1.1 --- Core Architecture --- p.74 / Chapter 6.2.1.2 --- Flow of Operation --- p.76 / Chapter 6.2.1.3 --- Data Replicator --- p.79 / Chapter 6.2.1.4 --- DCT Coefficients Memory --- p.80 / Chapter 6.2.2 --- Combination of IDCT to 1D DCT core --- p.82 / Chapter 6.2.3 --- Accuracy --- p.85 / Chapter 6.3 --- Transpose Memory --- p.87 / Chapter 6.3.1 --- Architecture --- p.89 / Chapter 6.3.2 --- Address Generator --- p.91 / Chapter 6.3.3 --- RAM Block --- p.94 / Chapter Chapter7 --- Results and Discussions --- p.97 / Chapter 7.1 --- Overview --- p.97 / Chapter 7.2 --- Refresh Control Circuit --- p.97 / Chapter 7.2.1 --- Implementation Results and Performance --- p.97 / Chapter 7.2.2 --- Discussion --- p.100 / Chapter 7.3 --- Programmable DSP Processor --- p.102 / Chapter 7.3.1 --- Implementation Results and Performance --- p.102 / Chapter 7.3.2 --- Discussion --- p.104 / Chapter 7.4 --- ID DCT/IDCT Core --- p.107 / Chapter 7.4.1 --- Simulation Results --- p.107 / Chapter 7.4.2 --- Measurement Results --- p.109 / Chapter 7.4.3 --- Discussion --- p.113 / Chapter 7.5 --- Transpose Memory --- p.122 / Chapter 7.5.1 --- Simulated Results --- p.122 / Chapter 7.5.2 --- Measurement Results --- p.123 / Chapter 7.5.3 --- Discussion --- p.126 / Chapter Chapter8 --- Conclusions --- p.130 / Appendix --- p.133 / Operations of switches in DCT implementation of programmable DSP processor --- p.133 / C Program for evaluating the error in DCT/IDCT core --- p.135 / Pin Assignments of the Programmable DSP Processor Chip --- p.142 / Pin Assignments of the 1D DCT/IDCT Core Chip --- p.144 / Pin Assignments of the Transpose Memory Chip --- p.147 / Chip microphotograph of the 1D DCT/IDCT core --- p.150 / Chip Microphotograph of the Transpose Memory --- p.151 / Measured Waveforms of 1D DCT/IDCT Chip --- p.152 / Measured Waveforms of Transpose Memory Chip --- p.156 / Schematics of Refresh Control Circuit --- p.158 / Schematics of Programmable DSP Processor --- p.164 / Schematics of 1D DCT/IDCT Core --- p.180 / Schematics of Transpose Memory --- p.187 / References --- p.191 / Design Libraries - CD-ROM --- p.197

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

Kwok Yan-lun Andy. / Thesis submitted in: November 2004. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 133-137). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgements --- p.iii / List of Figures --- p.vii / List of Tables and Examples --- p.x / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Motivation --- p.1 / Chapter 1.2. --- Objective and Approach --- p.4 / Chapter 1.3. --- Thesis Organization --- p.5 / Chapter 2. --- Related Work --- p.7 / Chapter 2.1. --- Coverage --- p.7 / Chapter 2.2. --- ASIP Design Methodologies --- p.8 / Chapter 2.3. --- Asynchronous Technology on Processors --- p.12 / Chapter 2.4. --- Summary --- p.14 / Chapter 3. --- Asynchronous Design Methodology --- p.15 / Chapter 3.1. --- Overview --- p.15 / Chapter 3.2. --- Asynchronous Design Style --- p.17 / Chapter 3.2.1. --- Micropipelines --- p.17 / Chapter 3.2.2. --- Fine-grain Pipelining --- p.20 / Chapter 3.2.3. --- Globally-Asynchronous Locally-Synchronous (GALS) Design --- p.22 / Chapter 3.3. --- Advantages of GALS in ASIP Design --- p.27 / Chapter 3.3.1. --- Reuse of Synchronous and Asynchronous IP --- p.27 / Chapter 3.3.2. --- Fine Tuning of Performance and Power Consumption --- p.27 / Chapter 3.3.3. --- Synthesis-based Design Flow --- p.28 / Chapter 3.4. --- Design of GALS Asynchronous Wrapper --- p.28 / Chapter 3.4.1. --- Handshake Protocol --- p.28 / Chapter 3.4.2. --- Pausible Clock Generator --- p.29 / Chapter 3.4.3. --- Port Controllers --- p.30 / Chapter 3.4.4. --- Performance of the Asynchronous Wrapper --- p.33 / Chapter 3.5. --- Summary --- p.35 / Chapter 4. --- Platform Based ASIP Design Methodology --- p.36 / Chapter 4.1. --- Platform Based Approach --- p.36 / Chapter 4.1.1. --- The Definition of Our Platform --- p.37 / Chapter 4.1.2. --- The Definition of the Platform Based Design --- p.37 / Chapter 4.2. --- Platform Architecture --- p.38 / Chapter 4.2.1. --- The Nature of DSP Algorithms --- p.38 / Chapter 4.2.2. --- Design Space of Datapath Optimization --- p.46 / Chapter 4.2.3. --- Proposed Architecture --- p.49 / Chapter 4.2.4. --- The Strategy of Realizing an Optimized Datapath --- p.51 / Chapter 4.2.5. --- Pipeline Organization --- p.59 / Chapter 4.2.6. --- GALS Partitioning --- p.61 / Chapter 4.2.7. --- Operation Mechanism --- p.63 / Chapter 4.3. --- Overall Design Flow --- p.67 / Chapter 4.4. --- Summary --- p.70 / Chapter 5. --- Design of the ASIP Platform --- p.72 / Chapter 5.1. --- Design Goal --- p.72 / Chapter 5.2. --- Instruction Fetch --- p.74 / Chapter 5.2.1. --- Instruction fetch unit --- p.74 / Chapter 5.2.2. --- Zero-overhead loops and Subroutines --- p.75 / Chapter 5.3. --- Instruction Decode --- p.77 / Chapter 5.3.1. --- Instruction decoder --- p.77 / Chapter 5.3.2. --- The Encoding of Parallel and Complex Instructions --- p.80 / Chapter 5.4. --- Datapath --- p.81 / Chapter 5.4.1. --- Base Functional Units --- p.81 / Chapter 5.4.2. --- Functional Unit Wrapper Interface --- p.83 / Chapter 5.5. --- Register File Systems --- p.84 / Chapter 5.5.1. --- Memory Hierarchy --- p.84 / Chapter 5.5.2. --- Register File Organization --- p.85 / Chapter 5.5.3. --- Address Generation --- p.93 / Chapter 5.5.4. --- Load and Store --- p.98 / Chapter 5.6. --- Design Verification --- p.100 / Chapter 5.7. --- Summary --- p.104 / Chapter 6. --- Case Studies --- p.105 / Chapter 6.1. --- Objective --- p.105 / Chapter 6.2. --- Approach --- p.105 / Chapter 6.3. --- Based versus Optimized --- p.106 / Chapter 6.3.1. --- Matrix Manipulation --- p.106 / Chapter 6.3.2. --- Autocorrelation --- p.109 / Chapter 6.3.3. --- CORDIC --- p.110 / Chapter 6.4. --- Optimized versus Advanced Commercial DSPs --- p.113 / Chapter 6.4.1. --- Introduction to TMS320C62x and SC140 --- p.113 / Chapter 6.4.2. --- Results --- p.115 / Chapter 6.5. --- Summary --- p.116 / Chapter 7. --- Conclusion --- p.118 / Chapter 7.1. --- When ASIPs encounter asynchronous --- p.118 / Chapter 7.2. --- Contributions --- p.120 / Chapter 7.3. --- Future Directions --- p.121 / Chapter A --- Synthesis of Extended Burst-Mode Asynchronous Finite State Machine --- p.122 / Chapter B --- Base Instruction Set --- p.124 / Chapter C --- Special Registers --- p.127 / Chapter D --- Synthesizable Model of GALS Wrapper --- p.130 / Reference --- p.133

So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9

Radio Frequency Identification (RFID) has received a great deal of attention in past decades. It is an automatic identification system by replying and retrieving data remotely using RFID transponders. Basically, RFID systems can be divided into three main categories: short transmission range, medium transmission range, and long transmission range. / Short and medium range RFIDs generally are passive transponders while long range RFID is of either passive or active type. In this thesis, a short transmission range RFID transponder is presented. This is a passive transponder which generates power for internal circuitry by inductive coupling. For automatic identification applications such as electronic money tickets, the requirements of endurance, weight, size as well as cost appeal to use passive transponder rather than active transponder. Researches on the passive transponders have created a great challenge for engineers in terms of the tradeoff between power constraints, processing power and data transmission range. / The presented RFID transponder system adheres to the ISO 14443 standard Type B specification communication interface, which operates at 13.56MHz carrier frequency with a maximum read range around 50 mm. This research implemented a low power, high security, and long read range RFID transponder. For the analog RF interface, a series of novel architectures are adopted to improve the data transmission range. The digital core in the presented crypto-processor for data security. The asynchronous architecture has the advantages of fast computation time, low power consumption and small area. These are the attractive reasons to implement the core processing units using an asynchronous architecture. / This RFID system was fabricated with a 0.35um two-poly four-metal standard CMOS process with the silicon area of 1516 um x 1625 um. The measurement results show that the analog RF interface can generate a maximum 5.45mW power while the digital core circuit consumes only 2.77mW. In the wireless communication tests, the transponder read range can reach as far as 50 mm. / Leung, Pak Keung. / "June 2008." / Adviser: Choy Chin Sing. / Source: Dissertation Abstracts International, Volume: 70-03, Section: B, page: 1847. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced. This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is not as sensitive to variability as synchronous, while fault tolerance allows continued functional operation in the presence of defects. GasP is a self-timed asynchronous design that provides high performance in a simple circuit. Quadded Logic, is a gate level fault tolerant methodology. This study presents Quadded GasP, a fault tolerant asynchronous design. This work demonstrates that Quadded GasP circuits continue to function within performance expectations when faults are present. The increased area and reduced performance costs of Quadded GasP area also evaluated. These results show Quadded GasP circuits are a viable option for managing process variation and defects. Application of these circuits will provide decreased development and test times, as well as increased yield.

Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the Asynchronous Research Center (ARC) at Portland State University we build distributed hardware systems using self-timed computation and delay-insensitive communication. Where appropriate, self-timed hardware operations can reduce average and peak power, energy, latency, and electromagnetic interference. Alternatively, self-timed operations can increase throughput, tolerance to delay variations, scalability, and manufacturability. The design of complex hardware systems requires design automation and support for test, debug, and product characterization. This thesis focuses on design compilation and test support for dataflow applications. Both parts are necessary to go from self-timed circuits to large-scale hardware systems. As part of the research in design compilation, the ARCwelder compiler designed by Willem Mallon (previously with NXP and Philips Handshake Solutions) was extended. The key to testing distributed systems, including self-timed systems, is to identify the actions in the systems. In distributed systems there is no such thing as a global action. To test, debug, characterize, and even initialize distributed systems, it is necessary to control the local actions. The designs developed at the ARC separate the actions from the states ab initio. As part of the research in test and debug, a special circuit to control actions, called MrGO, was implemented. A scan and JTAG test interface was also implemented. The test implementations have been built into two silicon test experiments, called Weaver and Anvil, and were used successfully for testing, debug, and performance characterizations.