Technology offers students and educators an uncharted digital landscape of possibilities. Some educators feel strongly that technology enhances the classroom; others feel that it doesn't necessarily improve traditional teaching methods, and some even feel that it is detrimental to students' ability to focus or engage in face-to-face conversations. My project focuses on critical dialogue as defined by various theorists, and explores whether or not secondary English classrooms that use iPads continue to use the dialogical methods as outlined by these theorists (most of which could not have foreseen today's technological advancements). By relying on these theorists and scholars to provide definitions and descriptions of dialogue and its benefits, I explain unique opportunities that the iPad offers students for dialogical learning in general. In particular, I describe ways educators can use iPads in the secondary English classroom that clearly overcome the potential disadvantages that concern some teachers.

This study examined whether gender stereotypes and tropes are still used in movies, through analyzing two popular film trilogies with an age difference of 20 years. Each trilogy’s protagonist and love interest were analyzed with the goal of determining how each character were potrayed. This study was seen through a gender perspective, and based on a structuralism approach. To answer the study’s research questions, Mulvey’s (1975) male gaze theory and Hall’s representation theory were used. The study had a qualitative approach and a discourse analysis was used as an method, and the analysis model Mise-en-scène (Selby & Cowdery, 1995) was used. Upon completion of the study, the following could be ascertained: first, gender stereotypes and tropes are still used in films. But has become better at be hidden into the plot. Second, each character was portrayed according to gender stereotypes as well as tropes. Finally, both similarities and differences could be established in the representation of each character. Where it was clear that even though Elle were the protagonist of one trilogy, it was still the man who controlled the relationship. The same thing was stated in the Spiderman trilogy.

The computational abilities of today's parallel supercomputers are often quite impressive, but these machines can be impractical for some researchers due to prohibitive costs and limited availability. These researchers might be better served by a more personal solution such as a "hardware acceleration" peripheral for a PC. FPGAs are the ideal device for the task: their configurability allows a problem to be translated directly into hardware, and their reconfigurability allows the same chip to be reprogrammed for a different problem. Efficient FPGA computation of parallel problems calls for cellular computing, which uses an array of independent, locally connected processing elements, or cells, that compute a problem in parallel. The architecture of the computing cells determines the performance of the FPGA-based computer in terms of the cell density possible and the speedup over conventional single-processor computation. This thesis presents the design and performance results of four computing-cell architectures. MULTIPLE performs all operations in one cycle, which takes the least amount of time but requires the most chip area. BIT performs all operations bit-serially, which takes a long time but allows a large cell density. The two other architectures, SINGLE and BOOTH, lie within these two extremes of the area/time spectrum. The performance results show that MULTIPLE provides the greatest speedup over common calculation software, but its usefulness is limited by its small cell density. Thus, the best architecture for a particular problem depends on the number of computing cells required. The results also show that with further research, next-generation FPGAs can be expected to accelerate single-processor computations as much as 22,000 times. / Master of Science

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<p>A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application.</p><p>These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area.</p><p>The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction.</p><p>The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.</p>

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.

Η παρούσα εργασία επικεντρώνει το ενδιαφέρον της στην προσέγγιση των ποιημάτων, τα οποία περιέχονται στα Κείμενα Νεοελληνικής Λογοτεχνίας της Α΄ τάξης του Γυμνασίου. Η προσέγγιση αυτή επιχειρείται σύμφωνα με τη «ρητορική εκδοχή» της Αναγνωστικής Θεωρίας, τη βάση της οποίας συγκροτούν οι θεωρίες των: Roman Jakobson, Paul de Man και Wayne Booth. Η βασική μας υπόθεση ότι η όλη προσέγγιση των ποιημάτων για την Α΄ τάξη του Γυμνασίου διέπεται και από τη «ρητορική εκδοχή», όχι μόνο από την «ερμηνευτική» που αναφέρει το Διαθεματικό Ενιαίο Πλαίσιο Προγράμματος Σπουδών (2002), επιβεβαιώθηκε. Από την ανάλυση του υλικού μας, το οποίο περιλαμβάνει δεκαεννέα (19) ποιήματα, προέκυψαν ορισμένα ενδιαφέροντα ευρήματα. Πιο συγκεκριμένα, η μελέτη μας εντόπισε ότι στα ποιήματα της Α΄ τάξης του Γυμνασίου υπάρχουν αρκετοί ρητορικοί τρόποι, όπως, η μετωνυμία, η προσωποποίηση, η ρητορική ερώτηση, το σύμβολο, η αλληγορία, η ειρωνεία, με κυρίαρχη, ωστόσο, τη μεταφορά. Επίσης, στα ποιήματα καταγράφηκαν οι έννοιες του υπονοούμενου συγγραφέα και του υπονοούμενου αναγνώστη, ενώ αρκετές από τις ερωτήσεις/εργασίες που συνοδεύουν κάθε ποίημα στο σχολικό βιβλίο παραπέμπουν σε μεγάλο βαθμό στις θεωρητικές θέσεις των τριών βασικών εκπροσώπων της «ρητορικής εκδοχής» της Αναγνωστικής Θεωρίας. Το κύριο συμπέρασμά μας είναι ότι η διδασκαλία της Λογοτεχνίας στη Δευτεροβάθμια Εκπαίδευση, συγκεκριμένα στην Α΄ τάξη του Γυμνασίου, αξιοποιεί εκτός από την «ερμηνευτική εκδοχή» και τη «ρητορική εκδοχή» της Αναγνωστικής Θεωρίας, εφόσον στηρίζεται και χρησιμοποιεί αρκετές από τις θέσεις, τους όρους και τις έννοιες που συναντούμε στις θεωρίες των βασικών εκπροσώπων της «ρητορικής εκδοχής». Η διαπίστωση αυτή μπορεί να διευρύνει και να εμπλουτίσει ουσιαστικά τις διδακτικές προσεγγίσεις της Λογοτεχνίας στη Δευτεροβάθμια Εκπαίδευση. / This paper focuses on the approach of the poems contained in the Texts of Modern Greek Literature, the A΄ class of the Gymnasium. This approach was attempted in accordance with the «rhetoric version» of Reader-Response Theory, the basis of which, is formed by theories of: Roman Jakobson, Paul de Man and Wayne Booth. Our basic assumption that the whole approach of the poems for the first grade of the High school is governed by the «rhetoric version», not only by the «hermeneutic», as described by the Curriculum (2002), confirmed. From the analysis of the material employed, which includes nineteen (19) poems, there are some interesting findings. More specifically, our study found that the poems of A΄ class of high school there are several rhetorical modes, such as metonymy, personification, rhetorical question, symbol, allegory, irony, principal, however, the metaphor. Also, the poems were recorded concepts of implied author and implied reader, while several of the questions/ tasks that accompany each poem in the text book refer largely to the theoretical positions of the three main representatives of the «rhetoric version» of Reader-Response Theory. The main conclusion is that the teaching of Literature in Secondary School, specifically in the first grade of high school, utilizes the «rhetorical version» of Reader-Response Theory, apart from the «hermeneutic» one, since it is based on and uses many of the views, terms and concepts encountered in the theories of fundamentals representatives of the «rhetorical version». This finding can broaden and enrich substantially the teaching approaches of Literature in Secondary Education.

This thesis deals with the design system for multiple integrals for diferential expression with space variables. Today, integration is one of engineering problems. Reader is acquainted with different method of integration, then with numerican integration and Taylor series. The practical aim of this work is to design software and hardware system of numerican integration multiple integrals.

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