In this study, we discussed the capacitance-voltage characteristics of the GaN MOS structure with surface treatment using low energy ion beam prior to the oxide deposition. We used the E-Beam evaporator which was equipped with the ion beam assisted deposition system that originally used for optical thin film deposition. Before depositing SiO2 the surface was treated by low energy Ar+ with different processing time inside the vacuum chamber around 10-6 torr. The purpose was to reduce the density of interface states and to explore the influence of C-V characteristics of the GaN MOS structure. We have measured the high frequency C-V curve, hysteresis, and also varied the delay time while measuring. Based on the measuring results, some useful parameters of the device were obtained. Found that the deep depletion phenomenon and hysteresis were easy seen in high frequency C-V measurement. To lower the interfacial states of the sample and shorten the processing time of the low energy ion beam treatment yielded the better result.But the surface was easily damaged when the processing time was prolonged.At last we added the capacitance-voltage study of the Si MOS structure with surface treatment using low energy ion beam, and the capacitance-voltage study of the InN MOS structure.

InN films were grown on Si(111) wafer with AlN buffer layer by plasma-assisted molecular beam epitaxy (PAMBE). The sample went through a conventional cleaning process which involved sequential rinsing in acetone (5 mins), isopropyl alcohol (5 mins), de-ionized water (5 mins), and blown dry with nitrogen before SiO2 deposited. We used E-beam to deposit SiO2 thin film on InN. Ohmic contact (Ti) was prepared by e-beam evaporation. The system used to measure the high-frequency and low-frequency consists of Keithley 590 analyzer and Quasistatic CV meter. At last we added the capacitance-voltage study of the Si MOS structure and the research of growing high quality AlN for high quality InN.

The method of C-V analysis is a powerful technique to determine the parameter of MOS (metal oxide semiconductor) structure. In this study, we fabricate the MOS structure with rf magnetron sputtering of Ta2O5 on n-ZnSe surface. The n-ZnSe¡¦s with various carrier concentrations have different electrical property. Interfaces of various Ta2O5/ZnSe have different properties, for examples flatband voltage, threshold voltage, the mobile oxide charge density, and the effective oxide charge concentration and etc. We find that the interfaces of the Ta2O5/ZnSe MOS structure have low mobile charges and interface trap charges. Thus Ta2O5/ZnSe MOS structure may be worthy to develop further.

ABSTRACT As MOSFET getting smaller, its silicon dioxide reaches physical limit. To continue its insulation and reasonable interface defects density, now, SiOxNy is the replace material to fill the transition term between SiO2 to high-k material. SiOxNy is made from silicon dioxide and silicon nitride in different scale. Due to the uncompleted of bonding, the device¡¦s reliability is dependent on defects. The discussion about defects will help us to change the growth conditions in process and avoid to produce these defects. We use PL and Raman spectrum to study the defects in SiOxNy and compare them under different process conditions especially on the change of defects. PL result on 6.2 nm film have a peak at 390 nm, and 40 nm film have peak at 535 nm. This mean that under these two process conditions the defect correspond to 3.18 eV is . The defect correspond to 2.37 eV is . In this thesis, we report formulations of how to calculate the parameters of MOS structure, using SiON/p-Si MOS structure as calculated sample. The carrier concentration were calculated and compared with the Hall results. The flat band voltage and threshold voltage were calculated and compared with measured C-V curves.

In this thesis, the dimension effects and reliabilities of the p-channel poly-Si TFTs for AMOLED are successfully characterized. We have measured and compared the electrical behaviors of devices to study dimension and temperature effects in this experiment. The influences on the narrow channel width effects are also discussed and explained. It is found that the devices with narrow channel width, exhibit promotional turn-on current and smaller threshold voltage. In addition, the stress effects in p-channel poly-silicon thin-film transistors are investigated and characterized with various applied voltages. The stress effects are clearly analyzed by different methods, such as activation energy of leakage current, changing the definition of source and drain for Vg-Id curve, and C-V measurements. Finally, a physical model was proposed to well explain the results we observed.

In the generation of deep submicron semiconductor fabrication¡Atransmission delay is primarily caused by the parasitic resistance and capacitance (RC) in the multilevel interconnects. Besides¡Aelectromigration is also a serious issue for the reliability of devices . There are two principle methods of reducing the RC delay. The first method is to replace the Al wires with Cu interconnects which supply lower resistivity and high resistance to electromigration. The second method is to use a lower dielectric constant material as the inter-metal dielectric. But in Copper metallization¡Athe key issue of this technology is the formation of a thin barrier layer for Cu on the surface of the SiC film to prevent the absorption of water and diffusion of Cu. In this study¡Awe employed films SiC base compounds to investigate their chemical bonds, I-V characteristics comparisons with Al and Cu gate. On the other hand, because of serious C-V hysteretic phenomena, we try to analyze and build up models. There five models is reasonable for our experiment: (1) mobile ions, (2) dielectric polarization, (3) carrier injection, (4) gate-electrons injection, and (5) bound charges. They happens in different materials and structures.

Part A of two Project Reports; Part B can be found at: http://hdl.handle.net/11375/17691 / <p>The annealing behaviour of 15N implanted, aluminum doped-SiC has been studied by measuring the differential capacitance as a function of applied bias. The samples were doubly implanted at 450°c with 45 Kev and 25 Kev ions, for a dose of 10^16/cm^2 at each energy.</p> <p> An n-i-p structure with a thick insulator region was found after annealing at 1000°c. The thickness of this i region could be substantially reduced with additional annealing at higher temperatures, and a fairly good n-p junction was obtained after 1480°c anneal.</p> <p> About 20-30% of the implanted nitrogen ions were found to be electrically active.</p> <p> The C-V behaviour was found to have large variations with the a.c. measuring frequency.</p> / Thesis / Master of Engineering (MEngr)

Les technologies de films minces sur isolant apparaissent comme des solutions fiables pour la nano électronique. Elles permettent de dépasser les limites des technologies sur substrat silicium massif, en autorisant de faibles tensions d’utilisation et un gain en énergie significatif. En effet, les transistors à semi-conducteurs à grille métallique (MOSFET) avec un substrat totalement déplété (FDSOI) conduisent à des courants de fuites faible et améliorent la variabilité ce qui permet de diminuer les tensions d’alimentation en particulier pour les applications SRAM. A partir du nœud 14 nm, les transistors peuvent intégrer un canal SiGe, le diélectrique high-k et la grille métallique. Tous ces nouveaux modules de procédés technologiques rendent l’analyse électrique des transistors MOS ainsi que sa corrélation avec la technologie plus compliquées. Ce travail de thèse propose plusieurs nouvelles méthodologies d’extraction automatique et statistique de paramètres pour les empilements MOS FDSOI avancées. Ces méthodologies sont toutes basées sur des mesures de capacité par rapport à la tension (C-V) rendant compte du couplage capacitif entre grille métallique, canal et substrat face arrière. Avec de telles caractéristiques C-V, des méthodologies fiables sont proposées pour l’épaisseur d’oxyde de grille équivalente (EOT), le travail effectif de la grille métallique FDSOI (WFeff), ainsi que d’autres paramètres comme les épaisseurs du canal (tch) et de l’oxyde enterré (tbox) ainsi que l’affinité électronique efficace (Xeff) du substrat face arrière qui inclut les différents effets électrostatique à l’œuvre dans l’oxyde enterré et à ses interfaces. Ces différentes méthodologies ont été validées par des simulations quantiques. La force de l’analyse expérimentale a été de contrôler la cohérence des extractions obtenues sur tout un ensemble de transistors MOS obtenus à partir de variation sur les différentes briques de base et de contrôler la cohérence des paramètres extraits. / .Thin film technologies appear as reliable solutions for Nano electronics to go beyond bulk silicon technology limits, allowing lower power bias and thus energy harvesting. Indeed, Metal Oxide Semiconductors transistors (MOSFETs) with fully depleted substrate (FDSOI for ’Fully Depleted Silicon On Insulator’) allow low static off-currents and variability improvement that enable the use of power supply biases lower than with bulk silicon, especially for SRAMs. From 14nm nodes, FDSOI generations are including SiGe channel, high-k dielectric and metal gate. All these new process modules required for technology improvement also significantly increase the complexity of the MOS devices electrical analysis and meanwhile its correlation with technology. This PhD study propose different novel methodologies for automatic and statistical parameter extraction of advanced FDSOI MOS gate stack. These methodologies are all based on capacitance versus voltage (C-V) characteristics, obtained for the capacitive coupling between metal gate, channel and back side. With such C-V characteristics, reliable methodologies are proposed, leading to the extractions of the equivalent oxide thicknesses (EOT), the effective work function of the FDSOI metal gate (WFeff), but also other parameters such as channel and buried oxide thicknesses (tch, tbox) and an effective electron affinity of the substrate well (Xeff) that includes all electrostatic effects in the buried oxide and at its interfaces. Moreover, quantum simulations are considered in order to validate the different methodologies. For experimental analysis, the study has considered coherence and complementarity of different test structures as well as the impact of back substrate polarization

¡@¡@Because of the poly-si thin film transistor have the advantage of high mobility, it can improve the analysis for the flat plan display. Using the above advantage can combine the integrated circuit as control IC and memory on the small panel to reduce the number between the switch circuits and the outside contacts. These precise circuits must be considering the photo current¡Bthermal effects and the parasitical capacitance more due to the influence of these precise circuits is more serious than the switch circuits. In my thesis, the research of the electrical characteristics of the newest excimer laser crystallize coplane poly-si thin film transistors ,and using the device length with width is 128um/6um and 128um/16um can be extracted that the environment of the facing illumination have the photo-leakage current than none illumination about four orders, and the photo-leakage current is not consider with any gate voltage. ¡@¡@With the discussion of the capacitance, the main point of my researches is to change different conditions to extract the gate to source capacitance (Cgs). In addition, the slight carriers may effect the devices with the high mobility system on panel (SOP) technology error, the temperature must be considered. ¡@¡@We find the mobility is bigger at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the linear region and the on current is lower at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the saturation region. Using some references and some models as the concepts can analysis some phenomenons I refer to above.

In this paper, we use a room temperature processing system, Liquid Phase Deposition(LPD) method, to grow silicon dioxide. The advantages are cheap equipment, low temperature growth, and no thermal stress. The quality is good enough to be used in IC devices. To inverstigate the properties of silicon Dioxide, we have done different physical and chemical test, including AES,TEM,FTIR,P-etch rate. We used the high frequency C-V curve to study the interface properties. The leakage current help to clarify the film quality. Moreover, we also discuss the growth mechanism in order to more understanding of LPD method.