In this study, metal-oxide-semiconductor (MOS) capacitances were prepared with rf magnetron sputtering of Ta2O5 on both n-type GaN and p-type GaN. And metal-insulator-semiconductor (MIS) capacitances were prepared with conjugated rigid-rod polymers PBT on n-type GaN. The processes of fabrication the diodes were shown, and the structures of MOS/MIS diodes were represented. Hysteresis was observed in high-frequency capacitance-voltage (C-V) measurements. And the hysteresis was changed with different scanning delay time on scanning step. They were ascribed to mobile charges and interface charges. The carrier concentration were calculated and compared with the Hall results. The flatband voltage and threshold voltage were calculated and compared with C-V curves which were measured.

This thesis will talk about the difference between c-plane and m-plane GaN. We use C-V measurement and try to find the difference from C-V result. We use atomic layer deposit (ALD) to deposit Al2O3 no n-Si (111), p-Si (111), c-GaN, m-GaN, c-InN and m-InN for making MOS structure. And use 100 kHz to measure high frequency C-V and charge-voltage method to measure quasi-static capacitance and leakage current. The process and how the instrument work will present in article. In Si (111) case, the flat-band voltage is far away from ideal value. This tells us charge in oxide. Result of quasi-static method shows interface state density is between 1011 cm-2¡DeV-1 to 1012 cm-2¡DeV-1. From Ref. 13, SiO2-Si system with 1011 cm-2 interface trap charge density for Si (111). We compare C-V carrier concentration with Hall carrier concentration and find some difference. We put C-V result of experiment and simulated with COX and Hall carrier concentration we measured. In GaN case, here is deep depletion in C-V result. And quasi-static result also shows deep depletion of GaN. This phenomenon means generate time of hole of n-type GaN is very long. And we use light to excite electron and hole and measure C-V for average surface density of state. The density of stay of Al2O3/m-GaN and Al2O3/c-GaN system is similar. Only appearance difference between Al2O3/m-GaN and Al2O3/c-GaN is position of flat-ban voltage. flat-ban voltage of c-GaN is more negative than m-GaN. For InN, we see ¡§the middle is lower than edge¡¨ curve. Recently, few group present complete C-V curve of InN. We can not sure whether we can use typical way to analyze this data.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

Le travail de la thèse proposé consiste à étudier, caractériser et modéliser la performance et la fiabilité de composants semi-conducteurs sous conditions extrêmes c’est à dire pendant et après que ces composants ont subi un stress électrique, un stress thermique voire les deux stress en même temps. Les composants semi-conducteurs que nous avons étudiés sont des modules photovoltaïques en silicium monocristallin pour des applications dans les énergies renouvelables. Dans cette étude, ces composants ont été soumis à plusieurs types de dégradations générant des défauts localisés dans la structure des composants. Dans un premier temps, des études approfondies des caractéristiques I(V) et C(V) et des paramètres électriques des modules solaires photovoltaïques ont été réalisées en testant une série de modules sous différentes conditions environnementales afin de fournir des données pertinentes pouvant être utiles pour l'évaluation des performances, la modélisation du fonctionnement et pour la mise en œuvre correcte et complète des modules photovoltaïques. Ces caractérisations ont été complétées par l’étude des défauts créés à l’interface et dans les structures des modules photovoltaïques par les différents stress sur la base de mesures effectuées sur ces mêmes cellules par la technique Deep Level Transient Spectroscopy (DLTS). Grâce à cette technique, nous avons identifié et localisé ces défauts au sein du composant, en déterminant leur énergie d’activation et leur section efficace de capture. Les résultats de notre étude montrent ainsi l’importance des conditions de fonctionnement sur les performances instantanées et sur le long terme des systèmes photovoltaïques. Ils peuvent être exploitables directement dans la conception même des modules silicium voire transposable, en suivant la méthodologie de l’étude que nous proposons à de nouvelles technologies de modules / The objective of this work aim to study the performance, reliability of semiconductor structures after their operation under extreme conditions, during and after electrical stress, thermal stress, and combined electro thermal stresses. The studied semiconductor structures are photovoltaic cells for applications in the field of renewable energies. These devices have been exposed to several types of degradation generating localized defects in the structures. The I (V) and C (V) characteristics and electrical parameters have been studied before and after each stress case. The Deep Level Transient Spectroscopy (DLTS) was used as advanced technique for tracking the defects created at the interface and in the bulk structures. The DLTS technique allows identifying and locating these defects within the devices, by determining their activation energy and their capture cross-Section

The work deals with the capacitance measurement of high-voltage PN junctions. The work is divided into theoretical and practical parts. The theoretical part presents insight into the fundamental properties of PN junctions and methods for measuring of the capacitance of PN junctions, primarily by C-V measurement. In the practical part, several kinds of measuring circuits are introduced and a suitable method of measurement is found. The calculations of basic parameters - the width of the base and resistivity are presented and discussed. The results were compared with the values obtained by calculation from the technological parameters of the junction.

During recent years the thickness of the gate oxide has been reduced considerably. The progressive miniaturization of devices has caused several phenomena to emerge such as quasi-breakdown, direct tunneling and stress induced leakage currents. Such phenomena significantly modify the performance of the scaled-down MOSFETs. As a part of this research work, an effort has been made to study the performance and characteristics of the thin Gate oxide for MOSFETs and Tunnel Oxide for Floating Gate (FG) MOS devices. The exponential dependence of tunnel current on the oxide-electric field causes some critical problems in process control. A very good process control is therefore required. This can be achieved by finding out the exact value of F-N tunneling parameter. This research work also is an effort of finding an accurate value for parameter B and its dependence on the oxide thickness as the device are scaled down to a level where the probability of Direct Tunneling mechanism gains more prominence. A fully automated Low Current Measurement workstation with noise tolerance as low as 10-15 A was set up as a part of this research. C-V and I-V curves were analyzed to extract, determine and investigate the oxide thickness dependence of F-N parameter B. For oxide thickness in the range10~13 nm, the parameter B ranged between 260 and 267. Thus it can be said that it is not sensitive to the change in oxide thickness in this range. However it was noticed that for thickness around 7nm wide variety of results were obtained for the Fowler-Nordheim parameter B (B ranged from 260 to 454). This can be attributed to the enhancement in the leakage current due to the direct tunneling. Hence to have tight control over VT for a NVM, new algorithms need to be developed for even better process control for oxide thickness in the range of 7 nm and below.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第15668号 / 工博第3326号 / 新制||工||1502(附属図書館) / 28205 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 木本 恒暢, 教授 和田 修己 / 学位規則第4条第1項該当

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.