In this dissertation, the combined optical link, where the baseband digital signal and wireless signal are transmitted simultaneously over a multi-mode fiber (MMF) using an VCSEL and received through a photoreceiver and a feed forward equalizer (FFE). For this hybrid optical link, a new type of combiner is developed using the multi-layer organic (MLO) process. For the overall link simulation, a rate-equation-based VCSEL model is developed with circuit components. This model describes the high-speed modulation characteristic as well as the thermal effect on the L-I (light vs. bias current) characteristic. Additionally, The FFE is developed to further extend a MMF distance by compensating differential modal delay (DMD) in MMF. Two different implementation approaches are taken for the FFE by passive LC ladder based delay line and active inductance peaking delay line structure. To overcome the voltage headroom limitation of the conventional Gilbert cell architecture, modified Gilbert cell is presented and implemented as a multiplier cell for both FFEs. The FFEs are fully integrated on a single chip and fabricated by a standard 0.18 ?m CMOS process. The developed FFE successfully rebuild the distorted signal form the MMF at 10 Gbps data rate.

Recently, there is growing interest in high speed circuits for broadband communication, especially in wired networks. As the data rate increases beyond 1 GB/s conventional materials used as communication channels such as PCB traces, coaxial cables, and unshielded twisted pair (UTP) cables, etc. attenuate and distort the transmitted signal causing bit errors in the receiver end. Bit errors make the communication less reliable and in many cases even impossible. The goal of this work was to analyze, and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 µm process and it is capable of compensating up to 20 dB’s of attenuation at 1.5625 GHz for 15 and 20 meters of RG-58 A/U coaxial cables. The equalizer is able to remove 0.5 UI ( 160 ps ) of peak-to-peak jitter and output a signal with 0.1 UI ( 32 ps ) for 15 meters of cable at 3.125 Gb/s. The equalizer draws 18 mA from a 1.8 V power supply which is lower than publications [1, 2] for CMOS transversal equalizers.

The first topic of this thesis presents a one-time programmable (OTP) ROM using a standard logic CMOS process. A high voltage is applied to the gate-oxide to breakdown the MOS in the ROM-cell. It results in a low resistance compared to that of unprogrammed cells. Therefore, we can realize an OTP ROM with this characteristic on a CMOS logic ASIC or SOC. The second topic is a DDFS (Direct Digital Frequency Synthesizer) implementation. A straight-line approximation algorithm for sinusoid with compensation is adopted in the proposed DDFS such that the accuracy could be maintained and the cost is reduced. Most important of all, the proposed CMOS OTP ROM is employed as the sinusoidal look-up ROM table to simplify the ROM fabrication without any additional process step.

A second-generation CMOS current controlled conveyor (CCCII) and a tunable IF bandpass filter based on the CCCII are developed. The high frequency property and the control ability of the current conveyor makes the bandpass filter tunable in the range between 55MHz~410MHz, which is suitable for the IF filter application that is around 200MHz~300MHz. The Q-factor is also tunable and has a maximum value up to 800.

A novel CMOS tunable bandpass filter and a novel voltage controlled oscillator are proposed. Both circuits are designed using the UMC 0.5£gm CMOS process parameters. The CMOS tunablebandpass filter is realised by using the intrinic parasitic capacitance of the MOS transistor. This filter has neither on-chip planar inductor nor poly-capacitance; therefore, the chip area is reduced. Simulation results show that the bandpass filter is tunable in the range between 190MHz and 347MHz. Therefore, the filter is suitable for the IF filter application that is between 200MHz and 300MHz. The Q-factor is also tunable and has a maximum value of 983. Applying the circuit of the bandpass filter, a second order voltage controlled oscillator is designed. Simulation results show that the voltage controllable oscillator is tunable in the range between 444MHz and 746MHz.

This thesis deals with two kinds of RF CMOS low noise amplifiers (LNA). The low power LNA and the image-reject LNA. The impact of gain, noise figure, and stability on RF CMOS image-reject LNA has been studied. Through this study, the fundamental properties of image-reject LNA can be understood by a simple but physical concept. A current-reuse RF CMOS source-degenerated cascode LNA is also presented, which adopts a combination of source-degenerated NMOS inverter and Cascode topology to improve gain and noise figure, the existent and well-studied technique from the design standpoint, makes optimization of the stage easy. A modification of the proposed architecture is also presented, which adopts internal filters to achieve the image rejection without additional image-reject filters that degrade both noise figure and power consumption. It will be a good candidate for low power implementation of CMOS RF-IC. Both circuits¡¦ parameters except noise figures are simulated using TSMC 0.25 um RF CMOS component models. The noise models considered here include induced gate noise, thermal noise and shot noise [5]. The current-reuse source-degenerated NMOS inverter LNA noise figure is 0.7 dB, forward gain is 16 dB, and IIP3 is -15 dBm. The low power image-reject LNA noise figure is 0.7 dB, forward gain is 16 dB, IIP3 is -16 dBm, and image rejection is 20 dB at 1.6 GHz. Both LNAs operate at 2.4 GHz and consume about 6 mA under a 2.5 V voltage supply.

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

Reconfigurable impedance matching networks are an integral part of multiband radio-frequency (RF) transceivers. They are used to compensate for the input/output impedance variations between the different blocks caused by switching the frequency band of operation or by adjusting the output power level. Various tuning techniques have been developed to construct tunable impedance matching networks employing solid-state p-i-n diodes and varactors. At millimeter-wave frequencies, the increased loss due to the low quality factor of the solid-state devices becomes an important issue. Another drawback of the solid-state tuning elements is the increased nonlinearity and noise at higher RF power levels. The objective of the research described in this thesis is to investigate the feasibility of using RF microelectromechanical systems (RF-MEMS) technology to develop reconfigurable impedance matching networks. Different types of tunable impedance matching networks with improved impedance tuning range, power handling capability, and lower insertion loss have been developed. Another objective is to investigate the realization of a fully integrated one-chip solution by integrating MEMS devices in standard processes used for RF integrated circuits (RFICs). A new CMOS-MEMS post-processing technique has been developed that allows the integration of tunable RF MEMS devices with vertical actuation within a CMOS chip. Various types of CMOS-MEMS components used as tuning elements in reconfigurable RF transceivers have been developed. These include tunable parallel-plate capacitors that outperform the available CMOS solid-state varactors in terms of quality factor and linearity. A tunable microwave band-pass filter has been demonstrated by employing the proposed RF MEMS tunable capacitors. For the first time, CMOS-MEMS capacitive type switches for microwave and millimeter-wave applications have been developed using TSMC 0.35-µm CMOS process employing the proposed CMOS-MEMS integration technique. The switch demonstrates an excellent RF performance from 10-20 GHz. Novel MEMS-based reconfigurable impedance matching networks integrated in standard CMOS technologies are also presented. An 8-bit reconfigurable impedance matching network based on the distributed MEMS transmission line (DMTL) concept operating at 13-24 GHz is presented. The network is implemented using standard 0.35-µm CMOS technology and employs a novel suspended slow-wave structure on a silicon substrate. To our knowledge, this is the first implementation of a DMTL tunable MEMS impedance matching network using a standard CMOS technology. A reconfigurable amplifier chip for WLAN applications operating at 5.2 GHz is also designed and implemented. The amplifier achieves maximum power gain under variable load and source impedance conditions by using the integrated RF-MEMS impedance matching networks. This is the first single-chip implementation of a reconfigurable amplifier using high-Q MEMS impedance matching networks. The monolithic CMOS implementation of the proposed RF MEMS impedance matching networks enables the development of future low-cost single-chip RF multiband transceivers with improved performance and functionality.

This thesis presents a new simulation model for floating gate transistor (FGMOS) in nanometer scale technology where the transistors suffer from non-negligible gate leakage current due to the very thin Silicon oxide (SiO2) layer. The new FGMOS simulation model is used for transient and DC simulation and with any industry standard simulators such as Spector and various SPICE programs (i.e. HSPICE, WinSPICE, etc.). This model can be used for any technology that has SiO2 thickness less than 3nm and suffer from gate leakage current with no changes to the model itself; however, minimal changes need to be done to the gate tunnelling cell to comply with the technology parameters where the gate tunnelling current exponentially increases as tox decreases.

In this thesis, novel direct-digital Quadrature Phase Shift Keying (QPSK) modulators are proposed in low-cost Complimentary Metal Oxide Semiconductor (CMOS) technology for radio frequency (RF) wireless applications. Direct-digital architectures have attracted much attention recently as they potentially offer significant cost savings and performance benefits. A new direct-digital QPSK modulator concept is introduced where the carrier is modulated directly by digital data using Pass-Transistor Logic (PTL) circuits for a small size and low power consumption. The concept is demonstrated through the design of an L-band modulator followed by an enhanced tunable S-band version. The proposed L-band modulator first generates all four quadrature phases of the carrier by using a 90° resistor-capacitor, capacitor-resistor (RC-CR) phase shifter followed by two 180° active baluns. One signal from the in-phase components and another from the quadrature-phase components are later selected by two PTL circuits according to the in-phase (I) and quadrature-phase (Q) digital data respectively. Finally the chosen signals are subtracted by a differential amplifier. The circuit has been experimentally demonstrated in a standard 0.18μm CMOS process, showing good performance at 1.7GHz with the data transmission rate and carrier rejection exceeding 20Mbps and 40dB respectively. The integrated circuit (IC) measures only 425μm by 850μm and consumes less than 43mW of power. A new S-band direct-digital QPSK modulator is introduced that offers even better performance and requires fewer components. An active balun first splits the carrier into a pair of balanced signals, which are then fed to a 90° RC polyphase network generating all four differential quadrature signals. Voltage-controlled NMOS resistors are used in the RC polyphase network to fine-tune it after fabrication for the lowest possible phase error. Finally, only one of the four differential quadrature signals is selected by a PTL circuit consisting of six NMOS switches, according to both I and Q digital data values. The circuit has been experimentally demonstrated in a standard 0.18μm CMOS process showing very good performance at 2.4GHz, with the data transmission rate exceeding 56Mbps. The IC measures 720μm by 888μm with an active area of only 505μm by 610μm, and consumes less than 33mW of power. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-09-26 15:42:15.243