Recently, there is growing interest in high speed circuits for broadband communication, especially in wired networks. As the data rate increases beyond 1 GB/s conventional materials used as communication channels such as PCB traces, coaxial cables, and unshielded twisted pair (UTP) cables, etc. attenuate and distort the transmitted signal causing bit errors in the receiver end. Bit errors make the communication less reliable and in many cases even impossible. The goal of this work was to analyze, and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 µm process and it is capable of compensating up to 20 dB’s of attenuation at 1.5625 GHz for 15 and 20 meters of RG-58 A/U coaxial cables. The equalizer is able to remove 0.5 UI ( 160 ps ) of peak-to-peak jitter and output a signal with 0.1 UI ( 32 ps ) for 15 meters of cable at 3.125 Gb/s. The equalizer draws 18 mA from a 1.8 V power supply which is lower than publications [1, 2] for CMOS transversal equalizers.

The goal of this dissertation is to provide a solution by using a low-cost and high-performance laser module package for the applications of high-speed optical communication, fiber-to-the-home (FTTH), and passive optical network (PON). A 10-Gb/s coaxial-type laser module, a 10-Gb/s bi-directional optical sub-assembly (BOSA) module, and a 4 channels x 10-Gb/s coarse wavelength division multiplexing (CWDM) laser module have been implemented for this study. The conventional TO-Can header suffers poor RF transmission characteristics without proper modification. The notch filter effect induced by the parasitic inductance of the long lead and wires is one of its major factors. The proposed coaxial laser module is fitted with a commercial TO-Can with an internal matching resistor of 18£[ to reduce the signal reflection. The comparison of small signal results between the theoretical and the experimental results shows good agreement. The proposed 10-Gb/s coaxial laser module implemented can achieve 31% mask margins with the OC-192 standard. For cost consideration, the structure of the proposed 10-Gb/s BOSA modules is adapted to the idea of the commercial low bit rate of 155-Mb/s or 1.25-Gb/s BOSA modules. The proposed BOSA modules show a clear opening eye diagrams at both their transmitter and receiver side. The power penalty with a 10-km SMF transmission is 0.5dB and the crosstalk penalty is 0.9dB. According to the experimental results, we have demonstrated successfully the high-performance and the low-cost of 10-Gb/s BOSA modules and verified the feasibility of the bi-directional architecture for use in the future¡¦s high-speed FTTH or PON network applications. The 4 channel x 10-Gb/s laser modules adapted the existing low-cost TO-Can laser and the CWDM techniques provide one of the solutions for the 40-Gb/s optical communication application. The proposed optical module operating at 10-Gb/s per channel can exceed a rate of over 30 km transmission at the bit-error-rate (BER) of 10-9, with an average system power penalty of 12 dB. The proposed high-performance 40-Gb/s CWDM module shows the low-cost possibility that ensures the application of WDM-passive optical network (WDM-PON) fiber-to-the-home (FTTH) systems.

A cost-effective 25 Gb/s directly-modulated transmitter optical sub-assembly (TOSA) packaging solutions by transistor outline (TO)-Can materials and processes were proposed and demonstrated. The purpose of this dissertation is to develop a high bandwidth TO-Can header for high-speed laser module, to verify a method, to propose a three-version of 25 Gb/s TO-Can laser module packaging, and to analyze in the frequency-domain and time-domain, and to experimentally demonstrate a 25 Gb/s TOSA. Usually, the transmission bandwidth of a conventional TO-Can laser module is limited below 10 GHz. To overcome this limitation and figure out the solution, firstly, the geometric structure of a conventional TO-56 header was analyzed by using transmission line models and electrical characteristics of the TO-56 header through a three-dimensional electromagnetism full-wave simulation software. The simulated results were in good agreement with the measured results and verify the applicability. Furthermore, we found that the 3-dB bandwidth of a conventional TO-56 header was limited at 16.7GHz. In this study, the first version of TO-Can header V1 was proposed to overcome the problem of the discontinuous impedance. By applying the TO-Can header V1, a TO-Can laser module package was proposed. The electrical characteristics parameters of the TO-Can header V1 were extracted and combined with small-signal equivalent circuit models of laser diode to simulate the electrical characteristics of the entire TO-Can laser module by the circuit simulation tool. Since bent inside feed-leads and two-step coaxial feed-through holes of the TO-Can header V1 were difficult to achieve in our laboratory equipments, the second version of TO-Can header V2 was proposed and verified experimentally. A 25 Gb/s TO-Can laser module with a matching resistor by adopting the TO-Can header V2 was proposed. The simulated results of this solution by considering with bonding-wires showed that the transmission bandwidth and eye diagram could achieve requirements of 25 Gb/s transmissions. Finally, the third version of 25 Gb/s TO-Can laser module adopted the TO-Can header V2 and an AlN submount of L-shaped microstrip line was proposed, fabricated, and measured. A DFB LD chip with a 3-dB bandwidth of 21.2 GHz was modeled and used in the simulation and the fabrication. Due to the parasitic effect induced by bonding-wires and die-bonding structure, the variation of high frequency performance of the laser module was simulated comprehensively. By referring to the proposed structure, a TOSA was fabricated by a conventional TO-Can and TOSA fabrication equipments and processes. The measured 3-dB bandwidth of the TOSA was 18.7 GHz. A clear eye diagrams of 25 Gb/s and BER testing for BTB and SMF transmission were obtained. This cost-effective solution of the TOSA is compatible with existing automatic TO-Can process lines and can be fabricated massively. Therefore, the results of this study of proposed TOSA can be applied in the next generation networks of 100GBASE-LR4, OTU4, and 32GFC. The presented simulation and verified technique may provide sufficient estimation and step-by-step analysis to assist the high-speed and high-density optical communication applications and various product developments in the future.

Tato diplomová práce se věnuje problematice VLSI návrhu a implementaci vrstvy RS-FEC pro 400 Gb/s Ethernet do FPGA Intel® Stratix® 10 DX 2100. V práci je charakterizován současný stav rychlostí Ethernetu, význam a kontext samoopravných kódů v rámci protokolu Ethernet. Dále je popsána výroba PLD čipů i matematická podstata RS sa moopravných kódů. V části praktické je představen návrh řešení systému RS-FEC, který byl realizován genericky pomocí jazyka VHDL. Zároveň byly jeho komponenty implementovány a v závěrečné diskusi je popsáno jeho řešení, dosažené výsledky včetně jeho budoucího rozšíření.

Recent advancements in silicon technology have paved the way for the development of integrated transceivers operating well inside the mm-wave frequency range (30 - 300 GHz). This band offers opportunities for new applications such as remote sensing, short range radar, active imaging and multi-Gb/s radios. This thesis presents new ideas at the circuit and system level for a variety of such applications, up to 145 GHz and in both state-of-the-art nanoscale CMOS and SiGe BiCMOS technologies. After reviewing the theory of operation behind linear and power amplifiers, a purely digital, scalable solution for power amplification that takes advantage of the significant ft/fmax improvement in pFETs as a result of strain engineering in nanoscale CMOS is presented. The proposed Class-D power amplifier, features a stacked, cascode CMOS inverter output stage, which facilitates high voltage operation while employing only thin-oxide devices in a 45 nm SOI CMOS process. Next, a single-chip, 70-80 GHz wireless transceiver for last-mile point-to-point links is described. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gbps. The high bitrate is accomplished by taking advantage of the ample bandwidth available at the W-band frequency range, as well as by employing a direct QPSK modulator, which eliminates the need for separate upconversion and power amplification. Lastly, the system and circuit level implementation of a mm-wave precision distance and velocity sensor at 122 and 145 GHz is presented. Both systems feature a heterodyne architecture to mitigate the receiver 1/f noise, as well as self-test and calibration capabilities along with simple packaging techniques to reduce the overall system cost.

Recent advancements in silicon technology have paved the way for the development of integrated transceivers operating well inside the mm-wave frequency range (30 - 300 GHz). This band offers opportunities for new applications such as remote sensing, short range radar, active imaging and multi-Gb/s radios. This thesis presents new ideas at the circuit and system level for a variety of such applications, up to 145 GHz and in both state-of-the-art nanoscale CMOS and SiGe BiCMOS technologies. After reviewing the theory of operation behind linear and power amplifiers, a purely digital, scalable solution for power amplification that takes advantage of the significant ft/fmax improvement in pFETs as a result of strain engineering in nanoscale CMOS is presented. The proposed Class-D power amplifier, features a stacked, cascode CMOS inverter output stage, which facilitates high voltage operation while employing only thin-oxide devices in a 45 nm SOI CMOS process. Next, a single-chip, 70-80 GHz wireless transceiver for last-mile point-to-point links is described. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gbps. The high bitrate is accomplished by taking advantage of the ample bandwidth available at the W-band frequency range, as well as by employing a direct QPSK modulator, which eliminates the need for separate upconversion and power amplification. Lastly, the system and circuit level implementation of a mm-wave precision distance and velocity sensor at 122 and 145 GHz is presented. Both systems feature a heterodyne architecture to mitigate the receiver 1/f noise, as well as self-test and calibration capabilities along with simple packaging techniques to reduce the overall system cost.

This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.

La théorie, la conception, l'optimisation et la caractérisation d'amplificateurs distribués en technologie TBDH InP 0,7 µm, pour les systèmes de communications optiques à 100 Gbit/s, sont présentés. Nous montrons comment l'exploitation adaptée du concept d'amplificateur distribué avec une technologie de transistors bipolaires à produit vitesse-amplitude élevé a permis la réalisation d'un driver de modulateur électro-optique fournissant une amplitude différentielle d'attaque de 6,2 et 5,9 Vpp, à 100 et 112 Gbit/s, respectivement, avec une qualité de signal élevée. Ce circuit établit ainsi le record de produit vitesse-amplitude à 660 Gbit/s.V sur tranche et 575 Gbit/s.V en module hyperfréquence. Dans le cadre du projet Européen POLYSYS, il a été associé à un laser accordable et un modulateur pour la réalisation d'un module transmetteur optoélectronique compact, démontrant des performances avançant l'état de l'art des communications optiques courtes distances à 100 Gbit/s. / The theory, design, optimisation and characterisation of distributed amplifiers in 0.7-µm InP DHBT technology, for 100-Gbit/s optical communication systems, are presented. We show how the appropriate implementation of the distributed amplifier concept in a bipolar transistors technology with high swing-speed product has enabled the realisation of an electro-optic modulator driver with 6.2- and 5.9-Vpp differential driving amplitude at 100 and 112 Gb/s, respectively, with a high signal quality. This circuit thus establishes the swing-speed product record at 660 Gb/s.V on wafer and at 575 Gb/s.V in a microwave module. In the frame of the European project POLYSYS, it has been co-packaged with a tunable laser and a modulator to realise a compact optoelectronic transmitter module, which has demonstrated performances advancing the state of the art of short reach 100-Gb/s optical communications.