No description available.

<p> Early detection of pathogens in food and water samples is essential in containing and preventing the spread of various diseases, such as campylobacter jejuni or E-coli. In the food processing industry, fast and reliable methods for testing products against contamination would mean faster delivery and better food quality. The pairing specificity of complementary DNA strands provides a highly selective means of detecting pathogens based on their genomic content. Recently, a lot of research has been directed towards the use of mainstream semiconductor technology to build highly sensitive and cheap DNA hybridization sensors. Typically, the gate of a metal-oxide-semiconductor (MOS) transistor is removed, and probe single-stranded DNA molecules are added to the exposed insulator. Complementary DNA hybridization from a solution sample can then be sensed electrostatically by the underlying Field-Effect transistor (FET). </p> <p> The work in this thesis is concerned with the mathematical modeling of FET based biosensors, named BioFETs. Modeling will enable the assessment of the sensitivity of such devices, as well as the potential for using the BioFETs in creating fully electronic microarrays. The mathematical model presented here captures the effects of ionic charge screening of the DNA charges by counterions in the ambient solution, and the effects of surface adsorption that can also aid in the charge screening process. The effects of varying different parameters on the sensitivity of the BioFET are investigated, and the noise contributed by the FET structure is incorporated into the analysis to quantify the expected signal-to-noise ratio (SNR) ofthe BioFET. </p> <p> In order to gain further insight into the operation of the BioFET, linear approximations are applied to the different regions of the BioFET to arrive at an analytic expression that approximates its expected response to DNA hybridization. The approximations are verified by comparing them against the results obtained from the physical model. Finally, different circuit configurations are presented that allow for highly sensitive biosensors to be realized using the BioFET, and a description of a fabricated electronic DNA microarray chip in standard CMOS 0.8 μm is presented. </p> / Thesis / Master of Applied Science (MASc)

<p> In past years, wireless technology has seen an incredible boom. As a result, industry has gone to great lengths to make wireless devices cheaper, smaller, faster and less power- hungry. This has prompted a significant interest in the research world to design circuit components that would facilititate these goals. However, much of the focus has been on wireless technology for communications applications, such as wireless telephony and wireless computer networking. More recently, there has been a focus on developing circuits for other wireless applications, one of which is wireless sensor networks. Such applications would demand extremely low-power operation, especially from the RF front-end. We have concentrated on achieving low-power operation for one of the important building blocks of the RF transceiver, which is the frequency downconversion mixer. </p> <p> In this thesis, we describe the design and results of two mixers, both designed in CMOS O.l8J.Lm technology offered by the Canadian Microelectronics Corporation (CMC). The first design uses the body terminal of the transistor as one of the inputs. This method allows for the radio-frequency (RF) and local oscillator (LO) stages in traditional switching mixers to be collapsed into one stage, thereby allowing for operation at lower supply voltages and lower power comsumption levels. This mixer was designed to downconvert a 1.9GHz RF signal to a 250MHz intermediate-frequency (IF) signal. The measured performance characteristics resulted in a power consumption of 400J.LW from a 0.8V supply, a conversion gain of 1dB, a single sideband (SSB) noise figure of 1ldB, and an input-referred 3rd-order intercept point (IIP3) of -9dBm. </p> <p> The second mixer design used a folding architecture to reduce the supply voltage headroom needed, as well as distribute the current appropriately for high-gain and lowpower operation. This mixer was designed to downconvert a 2.4GHz RF signal to a 100MHz IF signal. The simulated performance characteristics showed a power consumption of 640).1 W from a 1 V supply, a conversion gain of 4dB, a SSB noise figure of 19dB, and an IIP3 of -6.5dBm. </p> / Thesis / Master of Applied Science (MASc)

Le sujet de recherche prévoit l'amélioration des performances des inductances actives de type TOSI (transistor only simulated inductor), réalisées en technologie CMOS pour des applications de filtrage RF. Ces structures montrent de bien meilleures performances que les filtres classiques Gm–C par le petit nombre de transistors, la consommation d'énergie, la bande de fréquence et la surface du circuit intégré. En outre, les architectures TOSI peuvent être utilisées pour d'autres applications potentielles, comme les amplificateurs LNA et oscillateurs (VCO ou CCO). Dans le contexte du trend multi-standard suivi par les circuits de télécommunications (notamment sans fil), les filtres RF basés sur le concept TOSI offrent la possibilité de mise en œuvre des dispositifs accordables. pour répondre aux exigences des normes de télécommunications, la mise en œuvre des filtres d'ordre élevé est indispensable. Dans ce cas, l'utilisation de cellules de deuxième ordre est une question cruciale. Nos contributions les plus importantes présentées dans cette thèse consistent en un nouveau principe de réglage presque indépendamment de la fréquence de résonance et son facteur de qualité mais aussi sont proposées deux architectures de l'inductance TOSI avec une réponse améliorée en fréquence. D'autres résultats sont en cours de validation expérimentale. Nos travaux ont donné lieu à 12 articles publiés dans des revues prestigieuses ou présentés lors de conférences et workshops internationaux. En plus de ces aspects innovateurs, nous présentons dans ce mémoire un large descriptif des architectures des émetteurs-récepteurs sans fil utilisés pratique et un état de l'art des technologies et performances d'inductances TOSI proposées en technologie CMOS. / The scope of this thesis is to propose solutions to improve the performances of the CMOS transistor only simulated inductors (TOSI) aiming RF filtering applications. We are interested in TOSI architectures because they prove better performances than the classical gm–C filters, being superior with respect to the number of transistors, power consumption, frequency capability and chip area. Furthermore, TOSI architectures have many potential applications in RF design. In the general context of the multi–standard trend followed by wireless transceivers, TOSI based RF filters may offer the possibility of implementing reconfigurable devices. However, satisfying the telecommunications requirements is not an easy task therefore high order TOSI based filters should be implemented. Consequently, using good second order TOSI cells is a matter of the utmost importance and we propose a novel quality factor tuning principle which offers an almost independent tuning of self resonant frequency and quality factor for simulated inductors. An improved TOSI architecture with increased frequency capability is also reported.

Le développement de la radiocommunication sans fil et notamment, son explosion sur le marché grand public, a été rendu possible grâce au progrès du secteur de la microélectronique. En effet, l’intégration toujours croissante de fonctions au sein d’une même puce a permis le développement de ces nouvelles technologies basses consommations et à un moindre coût. Les travaux de recherche présentés dans ce manuscrit s’inscrivent dans le cadre de ces deux caractéristiques (faible coût et faible consommation). Nous avons donc développé deux solutions innovantes d’architectures radiofréquences : « half-complex » et « full-complex » en technologie CMOS. En effet, cette technologie représente la meilleure alternative car elle permet l’implémentation de fonctions RF analogique et numérique sur une même puce réduisant ainsi le coût du système. / Le développement de la radiocommunication sans fil et notamment, son explosion sur le marché grand public, a été rendu possible grâce au progrès du secteur de la microélectronique. En effet, l’intégration toujours croissante de fonctions au sein d’une même puce a permis le développement de ces nouvelles technologies basses consommations et à un moindre coût. Les travaux de recherche présentés dans ce manuscrit s’inscrivent dans le cadre de ces deux caractéristiques (faible coût et faible consommation). Nous avons donc développé deux solutions innovantes d’architectures radiofréquences : « half-complex » et « full-complex » en technologie CMOS. En effet, cette technologie représente la meilleure alternative car elle permet l’implémentation de fonctions RF analogique et numérique sur une même puce réduisant ainsi le coût du système.

Le standard LTE permet l’accès au très haut débit mobile et évolue afind’adresser les applications embarquées de type objets connectés. Mais dans la perspectived’un émetteur-récepteur LTE fabriqué dans une technologie CMOS faible-coût ethautement intégrable, l’amplificateur de puissance (PA) reste le seul bloc actif non intégréà ce jour. De plus, l’utilisation de modulations en quadrature oblige la conceptiond’amplificateurs très linéaires, générant une consommation statique plus importante.Dans ce contexte, ces travaux de thèse portent sur la recherche de composants etde circuits permettant d’atteindre de fortes puissances de sortie et de résoudre le compromisentre la linéarité et la consommation du PA. Deux axes de travail sont identifiéset développés dans cette thèse. Le premier axe porte sur l’utilisation d’un transistor depuissance intégrable en technologie CMOS. Trois cellules de puissance basées sur ce composantsont présentées, de l’étude théorique aux résultats de mesure. Dans le second axede recherche, ce transistor est intégré dans une architecture avancée de PA entièrementréalisée en CMOS. Une méthode de conception de transformateurs intégrés est égalementdéveloppée. Le PA proposé est reconfigurable pour adresser les différents besoinsimposés par le standard LTE : puissance de sortie, haute linéarité et faible consommation. / The LTE standard has been intended for mobile communications. Focusingnot only on higher data rate, LTE now aims at an implementation for the Internetof Things (IoT). The main challenge, in the perspective of a LTE front-end fully manufacturedin a low-cost and high integration level CMOS technology, remains the design ofpower amplifiers (PA). Furthermore, the use of complex quadrature modulation resultsin stringent linearity requirements resulting in an important quiescent dc consumption.In this context, this work focuses on the research of devices and circuits generatinghigh output power and solving the compromise between linearity and consumption ofthe PA. Two strands of work are identified and developed in this thesis. The first oneuses a power transistor available in CMOS technology. Three power cells based on thisdevice are proposed, with detailed theoretical and experimental results. In the secondone, this transistor is then used in a fully-integrated CMOS PA. A design methodologyfor integrated transformers is also presented. The proposed fully-integrated PA is reconfigurablein order to address the main LTE challenges : output power, high linearity andlow consumption.

Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 &#956m com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 &#956A de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3. / In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 &#956m technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 &#956A power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.

No intervalo de valores de frequência de poucos kHz até 1 MHz, nomeado às vezes como região de dispersão ?, as estruturas das células são o principal determinante da impedância do tecido. Esse é o fundamento básico da Espectroscopia da Bioimpedância Elétrica - EBE, a qual tem importância significativa como ferramenta de diagnóstico do câncer de colo no útero - CCU. A EBE consiste na medição de impedância elétrica do tecido cervical para diferentes valores de frequência. A diferença do comportamento no valor da impedância na frequência entre o tecido normal e o cancerígeno é usada para detectar o nível de neoplasia. Um bloco importante do Sistema EBE é o bloco gerador de sinal, o qual está composto principalmente de: a) Oscilador Controlado Numericamente - NCO, b) Conversor Digital - Analógico - DAC e c) Fonte de Corrente Controlada por Tensão - VCCS. O Objetivo do presente trabalho foi o projeto dos blocos principais do Gerador de Sinal para aplicação da Espectroscopia da Bioimpedância Elétrica na Detecção do Câncer no colo do Útero. O Gerador de Sinal é composto de: Oscilador Controlado Numericamente baseado no algoritmo de CORDIC, Conversor Digital - Analógico de 10 bits e Fonte de Corrente Controlada por Tensão. É apresentado o projeto do Oscilador Controlado Numericamente (NCO) de 10 bits baseado na arquitetura iterativa do CORDIC e otimizado em termos da área. O NCO foi implementado na Tecnologia CMOS do Processo da TSMC 180 nm por meio do FREE MINI@SIC IMEC-TSMC 2015. As especificações do projeto foram obtidas dos requerimentos da aplicação da Espectroscopia da Bioimpedância Elétrica - EBE na detecção do Câncer no Colo do Útero - CCU. A arquitetura proposta é composta fundamentalmente de: seletor de frequência de 5 bits, gerador do valor angular, bloco de pré-rotação, unidade aritmética do CORDIC, Unidade de Controle e tabela de busca da referência para arco-tangente. A área do núcleo para este componente foi de 133µmx133µm, ou seja, 0,017689 mm². Foi configurado para gerar 32 valores de frequência de sinais sinusoidais no intervalo de valores de frequência de 100 Hz até 1 MHz com um erro máximo de 0,00623% entre os valores de frequência obtidos da simulação e os resultados experimentais. O Conversor Digital - Analógico foi projetado no nível do esquemático numa arquitetura Current-Steering Segmentada 6-4 com valores de DNL<0,1 LSB e INL<0,2 LSB obtidos na análise de corners. O circuito VCCS foi projetado, simulado e fabricado em Tecnologia CMOS da TSMC 130 nm com polarização de 1,3 V. A Fonte de Corrente de Howland proposta foi baseada no amplificador operacional auto polarizado complementar de cascode dobrado (SB-CFC). De acordo com os requerimentos do padrão internacional IEC:60601-1 o valor pico da corrente sinusoidal foi ajustado em 10 µA. De acordo com aplicação da EBE para a CCD, as especificações do SB-CFC-AO foram calculadas para obter uma corrente sinusoidal na faixa de frequência de 100 Hz até 1 MHz com impedância de saída maior do que 1 MOhm a 1 MHz de frequência. Foram executadas simulações post-layout e os principais resultados foram: 10±0,0035 µA para a amplitude na corrente de saída na faixa de frequência especificada com 5 kOhm de resistência de carga, valores de impedância de saída maiores do 1,6 MOhm a 1 MHz; variações na amplitude da corrente de saída menores do que 0,4% para impedância de carga de 10 Ohm até 5 kOhm. O resultado experimental em termos de não-linearidade apresentou o máximo de 2% da plena escala. De acordo com os resultados obtidos, o desempenho do VCCS é adequado para aplicações da EBE na CCD. / In the frequency range of a few kHz to 1 MHz, sometimes referred to as the ? dispersion region, cell structures are the main determinant of tissue impedance. That is a basic fundamental of Electrical Bio-Impedance Spectroscopy - EBS, which has a significant importance as a diagnostic tool for Cervical Cancer Detection - CCD. EBS consists in the measurements of Electrical Impedance of cervical tissue at different values of frequency. The difference of behavior of impedance value in the frequency of normal tissue and cancerous tissue is used to detect the level of neoplasia. An important block of EBS System is the block signal generator, which is mainly composed of: a) Numerically Controlled Oscillator - NCO, b) Digital to Analog Converter - DAC and c) Voltage Controlled Current Source - VCCS. The aims of this work was to design the main blocks of a Signal Generator for Electrical Bio-Impedance Spectroscopy applied to Cervical Cancer Detection. The signal generator is composed by: CORDIC-Based Numerically Controlled Oscillator, 10-bits Digital-to-Analog Converter and Voltage Controlled Current Source - VCCS. A 10-bit Numerically Controlled Oscillator (NCO) based on the iterative architecture of COordinate Rotation DIgital Computer (CORDIC) optimized in terms of area is presented. The NCO was implemented in a TSMC CMOS 180 nm technology process on the FREE MINI@SIC IMEC-TSMC. The design specifications were obtained from the requirements for application of Electrical Bio-Impedance Spectroscopy (EBS) to Cervical Cancer Detection (CCD). The proposed architecture is basically composed by: 5-bit frequency selector, angle generator, pre-rotator block, CORDIC Arithmetic Unit, Control Unit and lookup table for arctangent reference. The area of this IC for the CORE circuit was 133µm X 133µm, i.e. 0,017689 mm². It was configured in order to generate 32 different frequencies for output sinusoidal signals in the frequency range of 100Hz up to 1MHz with maximum error of 0,00623% in frequency values obtained of comparison of theoretical and experimental results. The 10 bits DAC was implemented in a 6-to-4 Current Steering Segmented architecture with DNL<0,1 LSB and INL<0,2LSB obtained from corners analysis. The circuit VCCS was designed, simulated and fabricated in TSMC 130 nm CMOS technology at 1.3V power supply. The proposed Howland Current Source is based on Self-Biased Complementary Folded Cascode (SB-CFC) Operational Amplifier (OA). Complying with the requirements for medical electrical equipment of international standard ABNT-NBR-IEC-60601-1 the sinusoidal current peak amplitude was settled at 10 µA. In accordance with the requirements of the EBS for CCD, the specifications for the SB-CFC-OA were calculated to meet the 100 Hz to 1 MHz frequency range for the sinusoidal output current and the output impedance higher than 1 MOhm at 1 MHz frequency. Post-layout simulations were run and the main results were: 10 ± 0.0335 µA for the output current peak amplitude over the specified frequency range and with 5 kOhm load impedance; values above 1.6 MOhm output impedance @ 1 MHz; nominal current amplitude variations lower than 0.4% for load impedances in the range of 10 Ohm up to 5 kOhm. And the experimental result for maximum non-linearity was 2% of full scale. From these results, the performance of the VCCS is adequate for EBS-CCD applications.

A redução no consumo de potência em circuitos eletrônicos tem se tornado um dos requisitos mais importantes em projetos, especialmente com o recente aumento no número e na variedade de dispositivos móveis ou operados à bateria. Em tais dispositivos, o gerenciamento eficiente de energia é, muitas vezes, considerado mais importante que sua capacidade de processamento. Unidades lógico-aritméticas (ULAs) são componentes fundamentais em processadores, sendo responsáveis por executar as instruções que envolvem processamento numérico ou lógico. Normalmente, a ULA é o componente de maior consumo em um processador, o que a torna alvo de diversos estudos sobre técnicas para redução de consumo. Este trabalho apresenta um resumo sobre consumo de potência em circuitos digitais CMOS e as principais técnicas para sua redução, assim como os fundamentos para o projeto de ULAs, incluindo um estudo sobre algumas topologias para construção de somadores, deslocadores e multiplicadores e uma visão geral sobre a implementação de operações com números de ponto-flutuante e sobre a organização interna da ULA. É realizado o projeto de uma ULA de números inteiros de 16 bits em uma tecnologia CMOS de 0,35 \'mü\'m com aplicação de algumas das técnicas de redução de consumo apresentadas, que opera a uma frequência máxima de 212 MHz em tensão de alimentação de 3,3 V, consumindo, em média, 57 \'mü\'W e ocupando uma área de 0,121 \'MM POT.2\'. Este projeto é, ainda, comparado a uma ULA de referência, projetada na mesma tecnologia e com mesmas características funcionais, mas sem a utilização de quaisquer técnicas de redução de consumo. / The power consumption reduction in electronic circuits has turned one of the most important design requirements, especially with the recent increase of the number and variety of mobile or battery operated devices. In such devices, the efficient energy management is, many times, considered more important than its processing capability. Logic and arithmetic units (ALUs) are fundamental components in processors, being responsible for executing the instructions involving logic and numeric processing. Usually, the ALU is the most power consuming component in a processor, which makes it the target of several studies about power reduction techniques. This work presents a brief about power consumption in CMOS digital circuits and the major techniques for its reduction as well the fundamentals of ALU design, including a study about some topologies for adders, shifters and multipliers and a general view about floating-point number operations and about ALUs internal organization. It is realized the design of a 16-bit integer ALU in a 0,35 \'mü\'m CMOS technology with the application of some presented power reduction techniques that operates on a maximum frequency of 212 MHz on 3,3 V supply voltage, consuming, on average, 57 \'mü\'W and occupying an area of 0,121 \'MM POT.2\'. This design is also compared to a reference ALU, designed on the same technology and with same functional characteristics, but without using any power reduction techniques.

Geradores de referência, ou fontes de tensão de referência, são largamente empregados na composição de diversos circuitos eletrônicos, pois são responsáveis por gerar e manter uma tensão constante para o restante do circuito. Como se trata de um circuito analógico e que possui diversas condições a serem atendidas (baixo coeficiente de temperatura, baixa tensão de alimentação, baixa regulação de linha, dentre outras), sua complexidade é alta e isso se reflete no tempo/dificuldade de um projeto. Com a finalidade de aumentar a qualidade do circuito e diminuir o tempo de projeto, foi estudado o projeto de fontes de tensão de referência através da aplicação de metaheurísticas, que são métodos de otimização utilizados em problemas que não possuem solução analítica. As metaheurísticas aplicadas foram: algoritmos genéticos, simulated annealing e pattern search, todos disponíveis em uma toolbox de otimização do Matlab. A fonte projetada, utilizando uma topologia proposta neste trabalho, fornece uma tensão de referência de 0,302 V em 300 K a uma tensão mínima de operação de 1,01 V. O coeficiente de temperatura, no intervalo de -10°C a 90°C, é de 19 ppm/°C a 1,01 V e a regulação de linha, com tensão de alimentação no intervalo de 1,01 V a 2,5 V, é de 81 ppm/V a 300 K. O consumo de potência é de 4,2 \'mü\'W, também em 300 K e a 1,01 V e a área é de 0,061 \'MM POT.2\'. Como resultado, mostrou-se a eficiência da utilização destes métodos no dimensionamento de elementos do circuito escolhido e foi obtida uma fonte de tensão de referência que atende aos critérios estabelecidos e é superior quanto ao critério de regulação de linha, quando comparada a outras fontes da literatura. Neste trabalho, foi utilizada a tecnologia CMOS de 0,35 \'mü\'m da Austria Micro Systems (AMS). / Voltage references are widely employed to compose electronic circuits, since they are responsible for generating and maintaining a constant voltage to the rest of the circuit. As it is an analog circuit and it has several conditions to fulfill (low temperature coefficient, low supply voltage, low line regulation, among others), its complexity is high, which reflects at the time/difficulties of a design. In order to increase the quality of the circuit and to minimize the design time, it was studied voltage references design using metaheuristics, which are optimization methods used in problems with no analytical solution. The applied metaheuristics were: genetic algorithms, simulated annealing and pattern search, they are all available in an optimization toolbox at Matlab. The designed voltage reference, applying a topology proposed in this work, provides a reference voltage of 0.302 V at 300 K at a minimum supply voltage of 1.01 V. The temperature coefficient, from -10°C to 90°C, is 19 ppm/°C at 1.01 V and the line regulation, using a supply voltage from 1.01 V to 2.5 V, is 81 ppm/V at 300 K. The power consumption is 4.2 W also at 300 K and 1.01 V and the area is 0.061 \'MM POT.2\'. As a result, it was shown that those methods are efficient in sizing the devices of the chosen topology and it was obtained a voltage reference that fulfills all established criteria and that is superior at the line regulation criterion, when compared to other voltage reference of the literature. In this work, the 0.35-\'mü\'m CMOS technology provided by Austria Micro Systems (AMS) was used.