Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas. / This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells. / Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.

Mes travaux de thèse portent sur l'échantillonnage direct du signal RF en réception après l'antenne, dans un contexte d'applications radio-logicielle et radio-cognitive. Le but de cette technique est de pouvoir traiter le signal quelle que soit la modulation utilisée et dans une large gamme de fréquences, directement après l'antenne, en réduisant au maximum la partie analogique. Pour cela une architecture d'échantillonneur passif a été utilisée. L'originalité de cette architecture consiste en l'implémentation d'un système d'échantillonnage différentiel en quadrature purement passif, constitué d'un réseau de capacités commutées. En fixant la constante de temps du système à une valeur élevée devant la fréquence minimale du signal RF à démoduler, l'échantillonneur se comporte à la fois en tant que mélangeur et filtre en fréquence. Cela permet la réjection des brouilleurs hors de la bande de réception et contribue à améliorer sensiblement la dynamique du système de réception, le tout pour une consommation très faible. Aussi, le système est flexible en fréquence, permettant ainsi de recevoir le spectre RF sur une large bande et de recevoir différents types de signaux modulés. Celui-ci a été intégré dans un front-end de réception complet en technologie CMOS 130nm pour des applications dans les bandes ISM (433MHz et 868MHz) dont les débits de transmission sont limités à 1Mbits/s. L'architecture développée est adaptée à des applications de type radio-logicielle ou radio-cognitive, lorsqu'une agilité en fréquence, une grande dynamique et des contraintes de consommation très basse sont visées. / My thesis work is focusing on the RF signal direct sampling reception after the antenna in a software-defined radio applications and cognitive radio context. The purpose of this technique is to treat the signal whatever the modulation used and in a wide range of frequencies, directly after the antenna while minimizing at maximum the analog part. For this, a passive sampler architecture has been used. The originality of this architecture consists in the implementation of a passive differential sampling system working in quadrature, consisting of a switched capacitors network. By setting the time system constant to a high value compared to the minimum frequency of the RF signal to be demodulated , the sampler acts both as a filter and a frequency mixer. This allows the rejection of interferers outside the reception band and contributes to improve significantly the receiver system dynamic, for a very low consumption. Also, the system is flexible in frequency, which permits to receive the RF spectrum over a wide band of frequencies and detect different types of modulated transmitted signals. It has been integrated into a complete front-end 130nm CMOS technology receiver dedicated to ISM bands applications (433MHz and 868MHz bands) whose transmission data rates are limited to 1Mbit/s. The developed architecture is suitable for software-defined radio or cognitive radio applications where frequency agility, high dynamic and very low power constraints are targeted.

No intervalo de valores de frequência de poucos kHz até 1 MHz, nomeado às vezes como região de dispersão ?, as estruturas das células são o principal determinante da impedância do tecido. Esse é o fundamento básico da Espectroscopia da Bioimpedância Elétrica - EBE, a qual tem importância significativa como ferramenta de diagnóstico do câncer de colo no útero - CCU. A EBE consiste na medição de impedância elétrica do tecido cervical para diferentes valores de frequência. A diferença do comportamento no valor da impedância na frequência entre o tecido normal e o cancerígeno é usada para detectar o nível de neoplasia. Um bloco importante do Sistema EBE é o bloco gerador de sinal, o qual está composto principalmente de: a) Oscilador Controlado Numericamente - NCO, b) Conversor Digital - Analógico - DAC e c) Fonte de Corrente Controlada por Tensão - VCCS. O Objetivo do presente trabalho foi o projeto dos blocos principais do Gerador de Sinal para aplicação da Espectroscopia da Bioimpedância Elétrica na Detecção do Câncer no colo do Útero. O Gerador de Sinal é composto de: Oscilador Controlado Numericamente baseado no algoritmo de CORDIC, Conversor Digital - Analógico de 10 bits e Fonte de Corrente Controlada por Tensão. É apresentado o projeto do Oscilador Controlado Numericamente (NCO) de 10 bits baseado na arquitetura iterativa do CORDIC e otimizado em termos da área. O NCO foi implementado na Tecnologia CMOS do Processo da TSMC 180 nm por meio do FREE MINI@SIC IMEC-TSMC 2015. As especificações do projeto foram obtidas dos requerimentos da aplicação da Espectroscopia da Bioimpedância Elétrica - EBE na detecção do Câncer no Colo do Útero - CCU. A arquitetura proposta é composta fundamentalmente de: seletor de frequência de 5 bits, gerador do valor angular, bloco de pré-rotação, unidade aritmética do CORDIC, Unidade de Controle e tabela de busca da referência para arco-tangente. A área do núcleo para este componente foi de 133µmx133µm, ou seja, 0,017689 mm². Foi configurado para gerar 32 valores de frequência de sinais sinusoidais no intervalo de valores de frequência de 100 Hz até 1 MHz com um erro máximo de 0,00623% entre os valores de frequência obtidos da simulação e os resultados experimentais. O Conversor Digital - Analógico foi projetado no nível do esquemático numa arquitetura Current-Steering Segmentada 6-4 com valores de DNL<0,1 LSB e INL<0,2 LSB obtidos na análise de corners. O circuito VCCS foi projetado, simulado e fabricado em Tecnologia CMOS da TSMC 130 nm com polarização de 1,3 V. A Fonte de Corrente de Howland proposta foi baseada no amplificador operacional auto polarizado complementar de cascode dobrado (SB-CFC). De acordo com os requerimentos do padrão internacional IEC:60601-1 o valor pico da corrente sinusoidal foi ajustado em 10 µA. De acordo com aplicação da EBE para a CCD, as especificações do SB-CFC-AO foram calculadas para obter uma corrente sinusoidal na faixa de frequência de 100 Hz até 1 MHz com impedância de saída maior do que 1 MOhm a 1 MHz de frequência. Foram executadas simulações post-layout e os principais resultados foram: 10±0,0035 µA para a amplitude na corrente de saída na faixa de frequência especificada com 5 kOhm de resistência de carga, valores de impedância de saída maiores do 1,6 MOhm a 1 MHz; variações na amplitude da corrente de saída menores do que 0,4% para impedância de carga de 10 Ohm até 5 kOhm. O resultado experimental em termos de não-linearidade apresentou o máximo de 2% da plena escala. De acordo com os resultados obtidos, o desempenho do VCCS é adequado para aplicações da EBE na CCD. / In the frequency range of a few kHz to 1 MHz, sometimes referred to as the ? dispersion region, cell structures are the main determinant of tissue impedance. That is a basic fundamental of Electrical Bio-Impedance Spectroscopy - EBS, which has a significant importance as a diagnostic tool for Cervical Cancer Detection - CCD. EBS consists in the measurements of Electrical Impedance of cervical tissue at different values of frequency. The difference of behavior of impedance value in the frequency of normal tissue and cancerous tissue is used to detect the level of neoplasia. An important block of EBS System is the block signal generator, which is mainly composed of: a) Numerically Controlled Oscillator - NCO, b) Digital to Analog Converter - DAC and c) Voltage Controlled Current Source - VCCS. The aims of this work was to design the main blocks of a Signal Generator for Electrical Bio-Impedance Spectroscopy applied to Cervical Cancer Detection. The signal generator is composed by: CORDIC-Based Numerically Controlled Oscillator, 10-bits Digital-to-Analog Converter and Voltage Controlled Current Source - VCCS. A 10-bit Numerically Controlled Oscillator (NCO) based on the iterative architecture of COordinate Rotation DIgital Computer (CORDIC) optimized in terms of area is presented. The NCO was implemented in a TSMC CMOS 180 nm technology process on the FREE MINI@SIC IMEC-TSMC. The design specifications were obtained from the requirements for application of Electrical Bio-Impedance Spectroscopy (EBS) to Cervical Cancer Detection (CCD). The proposed architecture is basically composed by: 5-bit frequency selector, angle generator, pre-rotator block, CORDIC Arithmetic Unit, Control Unit and lookup table for arctangent reference. The area of this IC for the CORE circuit was 133µm X 133µm, i.e. 0,017689 mm². It was configured in order to generate 32 different frequencies for output sinusoidal signals in the frequency range of 100Hz up to 1MHz with maximum error of 0,00623% in frequency values obtained of comparison of theoretical and experimental results. The 10 bits DAC was implemented in a 6-to-4 Current Steering Segmented architecture with DNL<0,1 LSB and INL<0,2LSB obtained from corners analysis. The circuit VCCS was designed, simulated and fabricated in TSMC 130 nm CMOS technology at 1.3V power supply. The proposed Howland Current Source is based on Self-Biased Complementary Folded Cascode (SB-CFC) Operational Amplifier (OA). Complying with the requirements for medical electrical equipment of international standard ABNT-NBR-IEC-60601-1 the sinusoidal current peak amplitude was settled at 10 µA. In accordance with the requirements of the EBS for CCD, the specifications for the SB-CFC-OA were calculated to meet the 100 Hz to 1 MHz frequency range for the sinusoidal output current and the output impedance higher than 1 MOhm at 1 MHz frequency. Post-layout simulations were run and the main results were: 10 ± 0.0335 µA for the output current peak amplitude over the specified frequency range and with 5 kOhm load impedance; values above 1.6 MOhm output impedance @ 1 MHz; nominal current amplitude variations lower than 0.4% for load impedances in the range of 10 Ohm up to 5 kOhm. And the experimental result for maximum non-linearity was 2% of full scale. From these results, the performance of the VCCS is adequate for EBS-CCD applications.

Depuis la commercialisation du premier circuit intégré en 1971, l'industrie de la microélectronique s'est fixée comme leitmotiv de réduire les dimensions des transistors MOSFETs, en suivant la loi de Moore. Comme indiqué par Dennard, cette miniaturisation améliore automatiquement les performances des transistors. A partir des nœuds 28-22nm, les effets canaux courts sont trop difficiles à contrôler et de nouvelles architectures de transistors sont introduites: FDSOI pour STMicroelectronics, Trigate pour Intel. Dans ce contexte, l'évaluation des performances des technologies CMOS est clé et les travaux de cette thèse proposent de les évaluer au niveau circuit. Des modèles spécifiques d'estimation des paramètres électrostatiques et des capacités parasites sont développés. Ceux-ci sont d'abord utilisés sur des technologies amonts (co-intégration III-V/Ge et intégration 3D) puis sont implémentés en VerilogA pour être utilisés avec les outils conventionnel de CAO. Ceci fournit un modèle compact prédictif et utilisable pour toutes les architectures CMOS, qui est utilisé pour évaluer les performances logiques et SRAM des architectures BULK, FDSOI et Trigate aux nœuds 20nm et 16nm. / Since the commercialization of the first integrated circuit in 1971, the microelectronic industry has fixed as an objective to reduce MOSFET transistor dimensions, following Moore's law. As indicated by Dennard, this miniaturization automatically improves device performances. Starting from the 28-22nm technological nodes, short channel effects are to strong and industrial companies choose to introduce new device structure: FDSOI for STMicroelectronics and Trigate for Intel. In such a context, CMOS technology performance evaluation is key and this thesis proposes to evaluate them at circuit level. Specific models for electrostatic parameters and parasitic capacitances for each device structure are developed for each device structure. Those models have first been used to evaluate performances of advanced technologies, such as III-V/Ge co-integration and 3D monolithic integration and have then been implemented in VerilogA to ensure compatibility with conventional CAD tools such as ELDO. This provides a compact model, predictive and usable for each device structure, which has been used to evaluated logic and SRAM performances of BULK, FDSOI and Trigate devices for the 20nm and 16nm technology node.

Les nombreuses modifications de la structure du transistor bulk ont permis de poursuivre la miniaturisation jusqu'à sa limite aux nœuds 32/28nm. Les technologies actuelles répondent au besoin d'un meilleur contrôle électrostatique en s'ouvrant vers l'industrialisation de transistors complètement dépletés, avec les architectures sur film mince (FDSOI) ou non planaires (TriGate FinFET bulk). Dans ce dernier cas, le substrat bulk reste limitant pour des applications à basse consommation. La combinaison de la technologie SOI et d'une architecture non-planaire conduit aux transistors TriGate sur SOI (ou TGSOI). Nous verrons l'intérêt de ces dispositifs et démontrerons qu'ils sont compatibles avec les techniques de contrainte. On montrera en particulier les améliorations de mobilité et de courants obtenus sur ces dispositifs de largeur inférieure à 15nm. Des simulations montrent également qu'un dispositif TGSOI peut être compatible avec les techniques de modulation de VT. Enfin, nous démontrons la possibilité de fabriquer des dispositifs ultimes à nanofils empilés avec une grille enrobante par une technique innovante de lithographie tridimensionnelle. La conception, la caractérisation physique et les premiers résultats électriques obtenus seront présentés. Ces solutions peuvent répondre aux besoins des nœuds sub-10nm. / Changing the bulk transistor structure was sufficient so far to fulfill the scaling needs. The current technologies answer the needs of electrostatics control with the industrialization of fully depleted transistors, with thin-film (FDSOI) or non-planar (TriGate FinFet bulk) technologies. In the latter, bulk substrate is still an issue for low power applications. Combining SOI with multiple-gate structure gives rise to TriGate on SOI (or TGSOI). We will discuss the interest of such devices and will demonstrate their compatibility with strain techniques. We will focus on the mobility and current enhancement obtained on sub-15nm width devices. Simulations also demonstrate the compatibility of TGSOI with VT modulation technique. Finally, we demonstrate the fabrication through 3D lithography of ultimate stacked nanowires with a gate-all-around. The conception, physical characterization and first electrical results are presented.

L'avancement de la technologie durant ces dernières années a permis aux imageurs d'atteindre de très hautes résolutions. Ceci a rendu les images plus riches en détails. D'un autre côté, une autre limitation se présente à ce niveau; celle du nombre de bits limité après la conversion analogique numérique. De ce fait, la qualité de l'image peut être affectée. Pour remédier à cette limitation et garder une meilleure qualité de l'image en sortie de son système d'acquisition, l'information lumineuse doit être codée sur un grand nombre de bits et conservée durant tout le flot de traitement pour éviter l'intervention du bruit et la génération des artefacts en sortie du système. En outre, le traitement numérique de chaque pixel sera coûteux en consommation d'énergie et en occupation de surface silicium.Le travail effectué dans cette thèse consiste à étudier, concevoir et implémenter plusieurs fonctions et architectures de traitement d'image en électronique analogique ou mixte. L'implémentation de ces fonctions en analogique permet de décaler la conversion de l'information lumineuse en numérique vers une étape ultérieure. ceci permet de conserver un maximum de précision sur l'information traitée. Ces fonctions et leurs architectures ont un but d'améliorer la dynamique de fonctionnement des imageurs CMOS standard (à intégration), en utilisant des techniques à temps d'intégration variable, et des "tone mapping" locaux qui imitent le système de vision humaine.Les principes de fonctionnement, les émulations sous MATLAB, la conception et les simulations électriques ainsi que les résultats expérimentaux des techniques proposées sont présentés en détails dans ce manuscrit. / The technology progress in recent years has enabled imagers to reach a very high resolutions. This allows images to be more detailed and rich in information. On the other hand, the limited number of bites after the digital analogue conversion may drastically affect the quality of the image. To maintain the quality of the output image of the acquisition system, the luminous information should be (1) encoded on a large number of bits and (2) maintained throughout the processing flow so that to avoid noise interference and generating artifacts system output. However, the digital processing of each pixel will be energy consuming will occupy more surface silicon.The goal of this thesis is to study, design and implement several image processing functions as well as their architectures using analog and mixed electronic. Implementation of these functions shifts the analog to digital conversion to a subsequent step. This allows a maximum precision of the processed information. The proposed functions and their architectures improve the operational dynamics Standard CMOS imagers using (1) variable integration time techniques, and (2) "tone mapping" which mimics the human vision system.The experimental results based on emulations in Matlab and the electrical design show the novelty and the efficiency of the proposed method.

L'auteur n'a pas fourni de résumé en français. / Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device size, while embedding more and more complex functionalities in a single chip. However, the continuation of the device-scaling race generates a number of technology challenges. For instance, the downscaling of transistor channel lengths induce short-channel effects (drain-induced barrier lowering and punch-through phenomena); high electric field in the devices tend to increase Hot electron effect (or Hot Carrier) and Oxide Dielectric Breakdown; higher temperatures in IC products generates an increase of the Negative Bias Temperature Instability (NBTI) effect on pMOS devices. Today, it is considered that the above reliability mechanisms are ones of the main causes of circuit degradation performance in the field. This dissertation will address the Hot Carrier (HC) and NBTI impacts on CMOS product electrical performances. A CAD bottom-up approach will be proposed and analyzed, based on the Design–in Reliability (DiR) methodology. With this purpose, a detailed analysis of the NBTI and the HC behaviours and their impact at different abstraction level is provided throughout this thesis. First, a physical framework presenting the NBTI and the HC mechanisms is given, focusing on electrical parameters weakening of nMOS and pMOS transistors. Moreover, the main analytical HC and NBTI degradation models are treated in details. In the second part, the delay degradation of digital standard cells due to NBTI, HCI is shown; an in-depth electrical CAD analysis illustrates the combined effects of design parameters and HCI/NBTI on the timing performance of standard cells. Additionally, a gate level approach is developed, in which HC and NBTI mechanisms are individually addressed. The consequences of the degradation at system level are presented in the third part of the thesis. With this objective, data extracted from silicon measures are compared against CAD estimations on two complexes IPs fabricated on STCMOS 45nm technologies. It is expected that the findings of this thesis highly contribute to the understanding of the NBTI and HC reliability wearout mechanisms at the system level.STAR

Les récents progrès de fabrication des transistors en silicium-sur-isolant concernent la réduction de leurs dimensions, qui atteignent désormais quelques dizaines de nanomètres, et l'amélioration des contacts. Cela permet l'étude des premiers électrons du canal à basse température. Ceux-ci sont confinés dans les coins du nanofil, où le champ électrique est le plus intense. La dégénérescence de vallée du silicium est alors levée, donnant lieu à un singulet comme état à deux électrons de plus basse énergie en champ magnétique nul. La proximité de contacts quasi-métalliques permet l'étude des interactions entre ces électrons confinés et les électrons de la bande de conduction des contacts à travers l'effet Kondo et le Fermi-edge singularity.D'autre part les dopants, ingrédients essentiels de la fabrication de ces transistors, offrent naturellement une levée de dégénérescence de vallée de par leur fort potentiel de confinement. En variant le champ électrique transverse, nous étudions l'influence de l'environnement complexe sur l'ionisation d'un dopant selon sa position dans le canal. Nous avons ensuite réalisé le premier transistor à atomes couplés, où le transport est contrôlé par l'alignement des niveaux de deux atomes en série, facilitant la spectroscopie: nous mesurons une séparation entre les deux premiers états d'un dopant de l'ordre de 10 meV, un ordre de grandeur plus grand que celle des premiers électrons de la bande de conduction. Cette séparation permet de manipuler les états électroniques dans le régime de la dizaine de gigahertz. Une expérience d'interférométrie à un électron entre deux dopants est réalisée, ouvrant la voie vers des manipulations cohérentes dans des systèmes à dopants uniques. / Recent progress in Silicon-On-Insulator transistors fabrication have concerned a dimensions reduction, up to a few tens of nanometers, and an improvement of the leads. This allows to study the few electrons regime at low temperature. These latter are confined in the corners of the nanowire, where the electric field is maximized. This leads for the silicon valley degeneracy to be lifted, with a singlet for the two-electron ground state at zero magnetic field. We also investigate the interactions between these confined electrons and the electrons of the contacts conduction bands, with the Kondo effect and the Fermi-edge singularity.The dopants, essential ingredients of the transistors fabrication, naturally lift the valley degeneracy thanks to their deep confinement potential. First, by tuning the transverse electric field, we investigate the influence of the complex environment on a donor's ionization according to its position in the nanowire. We then realized the first Coupled-Atom Transistor, where the transport is controlled by the alignment of the ground states of two dopants placed in series. We could measure an energy splitting between the two first states of the order of 10 meV, one order of magnitude larger than that of the first electrons of the conduction band. This large separation allows to manipulate the electronic states in the ten's gigahertz regime. We induce one-electron interferences between the ground states of the two dopants, opening the way towards coherent electron manipulations in dopant-based devices.

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.