Gate-all-around (GAA) nanosheet field effect transistors (NSFETs) seem to be one of the most promising replacement options for FinFETs towards scaling down below to the sub-7nm technology nodes. They offer better electrostatics and control of short channel effects (SCEs) due to their superior control over the channel and their large effective channel width. Moreover, one can vertically stack multiple nanosheets to improve the drive strength of the device at a much-relaxed geometry than an aggressively scaled FinFET. However, stacking nanosheets would result in complex device structure, leading to significant process variability. Process variations could arise from irregular sheet thicknesses, random doping fluctuations, strain-induced variability, temperature effects, etc. which would affect the performance of the device. This has put a great emphasis on the need to come up with a properly calibrated process and simulation tools to analyze the performance of the NSFETs by identifying the sources of process variations with utmost precision. For this purpose, a TCAD-based simulation assessment has been done to model the design and performance of GAA NSFETs. The study explores the impacts of the variation in various physical parameters including the number of nanosheets, the sheet thickness, the work-function (WF) of metal gate stack layers, operational temperatures and channel doping on the electrical performance of the NSFETs. Moreover, a detailed fabrication process simulation flow for the design of a 3-sheet GAA NSFET has been presented. The simulation results predict that the process variations primarily have an impact on the device threshold voltage (Vth) which in turn influences the on-off currents, and the sub-threshold swing of the device. A comparative analysis has been done to understand the deviation of these electrical characteristics from their ideal values as a result of these variations. / Gate-all-around (GAA) nanoblads-fälteffekttransistorer (NSFETs) verkar vara ett av de mest lovande ersättningsalternativen för FinFET transistorer för att möjliggöra skalning ner till sub 7nm teknologinoderna. Denna typ av transistorer har bättre elektrostatik och kontroll av kortkanalseffekter (SCE) tack vare sin goda kontroll över kanalen och sin stora effektiva kanalvidd. Man kan dessutom stapla nanoblad vertikalt för att förbättra komponentens strömdrivningsförmåga med en mer relaxerad geometri än för en aggressivt skalad FinFET. Att stapla nanoblad gör komponentens struktur mer komplex vilket leder till betydande processvariabilitet. Processvariationer kan uppstå från oregelbundna tjocklekar för bladen, slumpmässiga dopningsfluktuationer, töjningsinducerad variabilitet, temperatureffekter m.m. Alla dessa variationer kan påverka komponentens prestanda. Det är därför viktigt att etablera korrekt kalibrerade process- och simuleringsverktyg för att analysera prestandan hos nanoblads-transistorerna. För detta ändamål har en TCAD-baserad simuleringsstudie gjorts för att modellera designen och prestandan för GAA nanoblads-transistorer. Studien undersöker effekterna av variationen i olika fysiska parametrar, inklusive antalet nanoblad och bladtjockleken, utträdesarbetet för metallgaten, temperaturen och kanaldopningen på den elektriska prestandan hos nanobladstransistorerna. Dessutom har ett detaljerat processimuleringsflöde för utformningen av 3-blads transistorer presenterats. Simuleringsresultaten visar att processvariationerna i första hand har en inverkan på transistorns tröskelspänning som i sin tur påverkar av- och på- strömmarna och subtröskelegenskaperna. En jämförande analys har gjorts för att förstå avvikelsen mellan dessa elektriska egenskaper från deras idealvärden som ett resultat av dessa variationer.

Les nombreuses modifications de la structure du transistor bulk ont permis de poursuivre la miniaturisation jusqu'à sa limite aux nœuds 32/28nm. Les technologies actuelles répondent au besoin d'un meilleur contrôle électrostatique en s'ouvrant vers l'industrialisation de transistors complètement dépletés, avec les architectures sur film mince (FDSOI) ou non planaires (TriGate FinFET bulk). Dans ce dernier cas, le substrat bulk reste limitant pour des applications à basse consommation. La combinaison de la technologie SOI et d'une architecture non-planaire conduit aux transistors TriGate sur SOI (ou TGSOI). Nous verrons l'intérêt de ces dispositifs et démontrerons qu'ils sont compatibles avec les techniques de contrainte. On montrera en particulier les améliorations de mobilité et de courants obtenus sur ces dispositifs de largeur inférieure à 15nm. Des simulations montrent également qu'un dispositif TGSOI peut être compatible avec les techniques de modulation de VT. Enfin, nous démontrons la possibilité de fabriquer des dispositifs ultimes à nanofils empilés avec une grille enrobante par une technique innovante de lithographie tridimensionnelle. La conception, la caractérisation physique et les premiers résultats électriques obtenus seront présentés. Ces solutions peuvent répondre aux besoins des nœuds sub-10nm. / Changing the bulk transistor structure was sufficient so far to fulfill the scaling needs. The current technologies answer the needs of electrostatics control with the industrialization of fully depleted transistors, with thin-film (FDSOI) or non-planar (TriGate FinFet bulk) technologies. In the latter, bulk substrate is still an issue for low power applications. Combining SOI with multiple-gate structure gives rise to TriGate on SOI (or TGSOI). We will discuss the interest of such devices and will demonstrate their compatibility with strain techniques. We will focus on the mobility and current enhancement obtained on sub-15nm width devices. Simulations also demonstrate the compatibility of TGSOI with VT modulation technique. Finally, we demonstrate the fabrication through 3D lithography of ultimate stacked nanowires with a gate-all-around. The conception, physical characterization and first electrical results are presented.

Depuis plus d'un demi-siècle, le monde de la microélectronique est rythmé par une course à la miniaturisation de son élément central, le transistor MOS, dans le but d'améliorer la densité d'intégration, les performances et le coût des circuits électroniques intégrés. Depuis plusieurs générations technologiques maintenant, la simple réduction des dimensions du transistor n'est plus suffisante et de nouveaux modules technologiques (utilisation de la contrainte, empilement de grille high-k/métal…) ont du être mis en place. Cependant, le transistor MOS conventionnel, même optimisé, ne suffira bientôt plus à répondre aux attentes toujours plus élevées des nouvelles technologies. De nouvelles architectures doivent alors être envisagées pour épauler puis, à terme, remplacer la technologie BULK. Dans ce contexte, cette thèse porte sur l'étude, la fabrication et la caractérisation électrique des architectures à film mince que sont le SOI localisé (ou LSOI) et le double grille planaire à grille enrobante (ou GAA). Les résultats obtenus mettent ainsi en évidence l'intérêt de ces dispositifs qui permettent une réduction du courant de fuite (et donc de la consommation), un excellent contrôle des effets électrostatiques et fonctionnent sans dopage canal (faible variabilité) tout en proposant de très bonnes performances statiques. L'impact d'une orientation de substrat (110) sur les propriétés de transport dans les transistors LSOI est également étudié. Ce travail de thèse garde comme ligne de mire la réalisation d'une plateforme basse consommation complète, impliquant une éventuelle intégration hybride avec des dispositifs BULK et la possibilité d'offrir plusieurs niveaux de tension de seuil, le tout sur une même puce. / For more than 50 years, microelectronic industry is driven by a race to the miniaturisation of its central element, the MOS transistor, to improve the integration density, the performances and the cost of the electronic integrated circuits. Since the adoption of 100nm node, the only reduction of the dimensions of the transistor is no more sufficient and new technological modules (use of strain, high-k/metal gatestack…) have been introduced. However, conventional MOSFET, even opimized, will soon be unable to reach the specifications, always higher, of new technologies. Then, new structures should be considered to help and, finally, to replace the BULK technology. In this context, the work concerns the study, the fabrication and the electrical characterization of the thin film devices : Localized-SOI (LSOI) and planar gate-all-around (GAA). The obtained resultats point out the interest of such devices which allow the reduction of the leakage current (and thus the consumption), an excellent control of electrostatics and are able to work with an undoped channel while offering very good static performances. Impact of (110) substrates on transport properties in LSOI transistors is also studied. This work focuses on the integration of a full low-power platform, what induces the possibility of an hybrid integration with BULK devices and to offer several threshold voltages, everything on the same chip.

Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.