Made available in DSpace on 2014-06-12T15:58:17Z (GMT). No. of bitstreams: 2 arquivo3360_1.pdf: 1861373 bytes, checksum: da4095d44ee2bf2199c241b47e6516e9 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010 / Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às tendências de mercado atuais, dispositivos portáteis, alimentados à bateria, estão sendo cada vez mais procurados, de modo que uma demanda de produtos que tenham uma maior capacidade de prolongar a vida útil das baterias vem crescendo. Recentemente, a redução do tamanho do transistor propiciou uma mudança no comportamento das componentes de energia em transistores CMOS. A componente estática que antigamente era praticamente desprezada tem aumentado exponencialmente com alterações não proporcionais, tais como diminuição do canal e redução de tensão de alimentação dos circuitos. Atualmente, esta componente estática representa uma fração significante da potência total consumida em circuitos com tecnologias de fabricação abaixo de 90 nm, podendo passar de 50% da potência total. Este consumo torna-se cada vez mais expressivo à medida que as tensões de alimentação dos circuitos são reduzidas, devido à necessidade de se minimizar a tensão de threshold para manter o desempenho dos circuitos. O algoritmo desenvolvido para a redução de potência estática em circuitos integrados digitais pode ser inserido no fluxo de desenvolvimento, sem causar penalidades ao mesmo. Na abordagem proposta, baseada na técnica Dual-Threshold, parte das células do circuito é substituída por células com tensão de threshold mais alta sem que haja inserção de violações de tempo no circuito. A troca de cada célula é definida a partir de estimativas do comportamento do circuito caso a célula seja trocada, antes que ela seja de fato substituída. Ao contrário de abordagens baseadas em caminhos, a característica de não haver trocas a cada análise das células do circuito, permite uma redução significativa no tempo de execução do algoritmo. Os resultados obtidos, que apresentaram uma redução de potência estática de até 39%, resultaram da execução do algoritmo utilizando circuitos do benchmark ISCAS85

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Résumé / Abstract

The aim of this work is to design and realise millimetre-wave low profile on-chip antennas for 60 GHz short-range wireless communication systems. For this application, it is highly desirable that the antenna can be compatible with standard silicon complementary metal oxide semiconductor (Si CMOS) technology for high level integration and mass production a low cost. Firstly, millimetre-wave antennas on normal dielectric substrates and cavities were studied in detail in order to better understand how the antenna parameters could have effects on their performance at millimetre-wave spectrum. On-chip 60 GHz antennas based on Si CMOS technology were then proposed, designed, fabricated and characterised. A millimetre-wave U-shaped slot antenna with wide bandwidth was first investigated, simulated and designed. The simulation results reveal that this antenna can operate at millimetre-wave frequencies with 1 GHz bandwidth at 73.5 GHz and 76.5 GHz, respectively. A 60 GHz folded dipole antenna was also studied and designed. A metal cavity was added on the back of a folded dipole antenna to act as reflector. Simulated results show that a folded dipole antenna with a metal cavity can achieve a radiation efficiency of 97.9% at its resonant frequency. Compared to the gain obtained for the folded dipole antenna without a cavity, the antenna gain with metal cavity can be enhanced by 3.58 dB. The main challenges of making high gain and high efficiency Si CMOS on-chip antennas at millimetre-wave spectrum come from two sources; the thin silicon dioxide (SiO2) layer (maximum 10 micrometre) and silicon substrate loss (10 ohmscm). The thin SiO2 layer prevents the use of an elevated ground plane, which could significantly reduce the silicon substrate loss, due to the imaging current effect. Si CMOS substrates normally have resistivity of 10 ohmscm, which is very lossy at millimetre-wave spectrum. To tackle these challenges, metamaterial structures, named artificial magnetic conductor (AMC) structures, were studied and utilised for low profile Si CMOS on-chip antenna design and realisation. AMC forms high impedance on its surface, reflecting the incident wave without phase reversal so as to enhance the radiation efficiency. The AMC folded dipole antenna was designed with a mushroom-shaped structured metamaterial cavity. Simulation results show that the gain increased 1.5 dB in the antenna with AMC structure, while the distance to the metamaterial surface was reduced by 90% compared to that of the pure metal cavity. Additionally, two low profile Si CMOS on-chip antennas with novel planar AMC structures were designed, fabricated and characterised. They were manufactured by 0.13 μm Si CMOS technology from Chartered foundry and 0.18 μm Si CMOS technology from TSMC, respectively. The techniques proposed in these two antennas provide valuable alternatives to the existing approaches. The measurement results show that bandwidth of the on-chip antenna with a micro-patterned artificial lattice is approximately 10 GHz. The one with a dog-bone shape and uniplanar compact photonic band gap (UC-PBG) structures managed a 1.6 dB gain and 1 GHz bandwidth enhancement compared to that without AMC structures.

Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which forms the main memory of digital computers. The ability of the sense amplifier to detect and amplify voltage signals to correctly interpret data in DRAM cells cannot be understated. The sense amplifier plays a significant role in the overall speed of the DRAM. Sense amplifiers require matched transistors for optimal performance. Hence, the effects of mismatch through process variations must be minimized. This thesis presents a research which leads to optimal nanoscale CMOS sense amplifiers by incorporating the effects of process variation early in the design process. The effects of process variation on the performance of a standard voltage sense amplifier, which is used in conventional DRAMs, is studied. Parametric analysis is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The figures-of-merit (FoMs) used to characterize the circuit are the precharge time, power dissipation, sense delay and sense margin. Statistical analysis is also performed to study the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. A design flow algorithm incorporating dual oxide and dual threshold voltage based techniques is used to optimize the FoMs for the sense amplifier. Experimental results prove that the proposed approach improves precharge time by 83.9%, sense delay by 80.2% sense margin by 61.9%, and power dissipation by 13.1%.

Binary multiplier has been a staple in the digital circuit design. It is used in microprocessor design, DSP applications etc. Here, we discuss the design of a novel multiplier that employs a modified shift and add logic to multiply two n-bit unsigned binary numbers. In our work, we changed the shift and add algorithm. We used a barrel shifter and a multiplexer to generate the partial products. We also found out a way to reduce the number of partial products so that we would have fewer numbers to add after we generated all of them. An array of Carry Save Adders (CSA) is used to add the partial products. With all our arrangements and setups, we aim to reduce delays and make the design as efficient as possible. As examples, we have shown it to multiply two 16-bit numbers, however, the design can easily be either scaled up or down according to the environment the multiplier is being used.

AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis Themistoklis The easy usage and less standby leakage are the main reasons SRAMs are mostly used for mobile applications both on chip and off chip memories. Various SRAM cells have been under research for many years. In post-CMOS era, rising of memristor technology is expected to be a key driver due to its outstanding features to replace the present memory technologies. Memristor is a non-volatile component that memorizes the proportion of current passed through it, reserving the data in the form of resistance. With its non-volatile characteristics, ultra-low power consumption, higher density capability, fast operating speed, ability to function as a multi-level cell and good scalability and compatibility with CMOS technology, memristor technology is found to be best to replace the SRAM cells. Memristor based SRAM cell can be an efficient circuit component that is being proposed in this thesis which consumes less power and allows the conventional SRAM cell to retain data with lesser number of transistors at power-down without any auxiliary circuit. This thesis contains the operating procedure and simulated results of the proposed four transistor and two memristor SRAM using 90nm technology performed on Cadence Virtuoso tool.

Modern consumer electronic systems are mostly based on analog and digital circuits and are designed as analog/mixed-signal systems on chip (AMS-SoCs). the integration of analog and digital circuits on the same die makes the system cost effective. in AMS-SoCs, analog and mixed-signal portions have not traditionally received much attention due to their complexity. As the fabrication technology advances, the simulation times for AMS-SoC circuits become more complex and take significant amounts of time. the time allocated for the circuit design and optimization creates a need to reduce the simulation time. the time constraints placed on designers are imposed by the ever-shortening time to market and non-recurrent cost of the chip. This dissertation proposes the use of a novel method, called metamodeling, and intelligent optimization algorithms to reduce the design time. Metamodel-based ultra-fast design flows are proposed and investigated. Metamodel creation is a one time process and relies on fast sampling through accurate parasitic-aware simulations. One of the targets of this dissertation is to minimize the sample size while retaining the accuracy of the model. in order to achieve this goal, different statistical sampling techniques are explored and applied to various AMS-SoC circuits. Also, different metamodel functions are explored for their accuracy and application to AMS-SoCs. Several different optimization algorithms are compared for global optimization accuracy and convergence. Three different AMS circuits, ring oscillator, inductor-capacitor voltage-controlled oscillator (LC-VCO) and phase locked loop (PLL) that are present in many AMS-SoC are used in this study for design flow application. Metamodels created in this dissertation provide accuracy with an error of less than 2% from the physical layout simulations. After optimal sampling investigation, metamodel functions and optimization algorithms are ranked in terms of speed and accuracy. Experimental results show that the proposed design flow provides roughly 5,000x speedup over conventional design flows. Thus, this dissertation greatly advances the state-of-the-art in mixed-signal design and will assist towards making consumer electronics cheaper and affordable.

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