Diese Dissertation untersucht das selektive Wachstum von Indiumphosphid (InP)-Nanostrukturen auf Silizium-Nanospitzen-Substraten (Si NT) mittels Gasquellen-Molekularstrahlepitaxie über den Nanoheteroepitaxie-Ansatz (NHE). Durch Anpassung der thermischen Reinigungstemperaturen vor dem Wachstum wurde der Übergang zwischen 1-dimensionalem Nanodraht- (NW) und 3-dimensionalem Nanoinselwachstum auf demselben Wafer demonstriert. Diese Anpassungsfähigkeit ist entscheidend für die Realisierung maßgeschneiderter nanoskaliger Halbleiterbauelemente. Die strukturellen und optischen Eigenschaften von NWs, die auf Si NT(001)-Substraten gewachsen sind, wurden umfassend analysiert. Diese NWs zeigten Polytopie mit sowohl Wurtzit- als auch Zinkblende-Kristallstrukturen und einer Typ-II-Bandausrichtung und wiesen Lumineszenz bei Raumtemperatur auf. Nanoinsel-Proben, die auf Si(001)- und Si(111)-Nanospitzen-Substraten gewachsen sind, behielten eine Zinkblende-Struktur bei und waren vollständig entspannt, was mit den jeweiligen Substraten übereinstimmte. Diese Nanoinseln wiesen jedoch keine Lumineszenz bei Raumtemperatur auf, was auf einen Verbesserungsbedarf des Materials hinweist. Die Wachstumsoptimierung für Nanoinseln auf Si NT(001)-Substraten ergab einen idealen Temperaturbereich von 490°C bis 530°C mit einem konstanten Phosphin-Fluss von 4 sccm und einer Wachstumsrate von 0,7 Å/s, was zu reproduzierbaren und hochwertigen Ergebnissen führte. Ein Testbauelement, das mit n-p dotierten InP-Nanoinseln gefertigt wurde, wurde hinsichtlich seiner elektrischen Eigenschaften bewertet, um seine Integration in funktionale Halbleiterbauelemente zu untersuchen. Insgesamt erweitert diese Arbeit das Verständnis des InP-Nanostruktursyntheseprozesses auf Si NT-Substraten mittels NHE und hebt ihr Potenzial für zukünftige Halbleitertechnologien, insbesondere für CMOS-kompatible Anwendungen, hervor. / This thesis investigates the selective growth of Indium Phosphide (InP) nanostructures on Silicon nanotip (Si NT) substrates using gas-source molecular beam epitaxy via the nanoheteroepitaxy (NHE) approach. By adjusting thermal cleaning temperatures prior to growth, the transition between 1-dimensional nanowire (NW) and 3-dimensional nanoisland growth on the same wafer was demonstrated. This adaptability is essential for realizing customized nanoscale semiconductor devices. The structural and optical properties of NWs grown on Si NT(001) substrates were thoroughly analyzed. These NWs exhibited polytypism, featuring both wurtzite and zincblende crystal structures with a type-II band alignment, and showed luminescence at room temperature. Nanoisland samples grown on Si(001) and Si(111) nanotip substrates retained a zincblende structure and were fully relaxed, aligning with their respective substrates. However, these nanoislands did not exhibit room-temperature luminescence, indicating a need for further material improvement. Growth optimization for nanoislands on Si NT(001) substrates identified an ideal temperature range of 490°C to 530°C with a constant phosphine flux of 4 sccm and a growth rate of 0.7 Å/s, ensuring reproducible, high-quality results. A test device fabricated using n-p doped InP nanoislands was assessed for electrical properties to explore their integration into functional semiconductor devices. Overall, this work advances the understanding of InP nanostructure synthesis on Si NT substrates via NHE and highlights their potential for future semiconductor technologies, particularly for CMOS-compatible applications.

A novel MOSFET gas sensor for the investigation has been developed. Its configuration resembles a"normally on"n-type thin-film transistor (TFT) with a gas sensitive metal oxide as a channel. The device used in the experiments only differs from common TFTs in the gate configuration. In order to allow gas reactions with the SnO2-surface, the gate is buried under the semiconducting layer. Without any gate voltage, the device works as a conventional metal oxide gas sensor. Applied gate voltages affect the channel carrier concentration and surface potential of the metal oxide, thus causing a change in sensitivity. The results of the gas measurements are in accordance with the electric adsorption effect, which was postulated by Fedor Wolkenstein 1957, and arises the possibility to operate a semiconductor gas sensor at relatively low temperatures and, thereby, be able to integrate CMOS electronics for processing of measurements at the same chip.

<p>A novel MOSFET gas sensor for the investigation has been developed. Its configuration resembles a"normally on"n-type thin-film transistor (TFT) with a gas sensitive metal oxide as a channel. The device used in the experiments only differs from common TFTs in the gate configuration. In order to allow gas reactions with the SnO2-surface, the gate is buried under the semiconducting layer. Without any gate voltage, the device works as a conventional metal oxide gas sensor. Applied gate voltages affect the channel carrier concentration and surface potential of the metal oxide, thus causing a change in sensitivity. The results of the gas measurements are in accordance with the electric adsorption effect, which was postulated by Fedor Wolkenstein 1957, and arises the possibility to operate a semiconductor gas sensor at relatively low temperatures and, thereby, be able to integrate CMOS electronics for processing of measurements at the same chip.</p>

The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications. Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study. A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications. Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed. Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated. Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis. The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.

Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world. / Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala. / <p>20170519</p>

Ces dix dernières années, les technologies de stockage non-volatile Flash ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimedia (MP3, Smartphone, clés USB, ordinateurs ultraportables…). Afin d’améliorer davantage les performances, augmenter les capacités et diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd’hui étudiées pour pouvoir compléter ou remplacer la technologie Flash. Citées par l’ITRS, les mémoires résistives polymères présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d’intégration haute densité au dessus des niveaux d’interconnexions CMOS ou sur substrat souple. Ce travail de thèse a été consacré au développement et à l'étude des mémoires résistifs organiques à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Trois axes de recherche ont été menés en parallèle: le développement et la caractérisation physico-chimique de matériaux composites, l’intégration du matériau organique dans des structures de test spécifiques et la caractérisation détaillée du fonctionnement électrique des dispositifs et des performances mémoires. / Over the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis.