OF MASTER THESIS Author: Bc. Kateřina Králová Supervisor: MUDr. Tereza Gueye Title of master thesis: Evaluation of Occupational Therapy Intervention in Acute Inpatient Rehabilitation of Cerebrovascular Units Abstract This diploma thesis deals with the evaluation of occupational interventions on the specific separation of beds of early rehabilitation of the cerebrovascular center of the General University Hospital in Prague. The subject of interest is primarily the results of the assessment obtained through the Functional Independence Measure (FIM) and the Montreal Cognitive Assessment. The thesis has two main objectives, namely mapping and analyzing the tools used to assess self-sufficiency and cognitive functions in the department. You can find the description of the evaluation tools in the theoretical part of the thesis. It is also an overview of the topic of the selected topic and a brief description of the system of cerebrovascular care in the Czech Republic. The second objective was to evaluate variables such as length of hospitalization and cognitive status in relation to patient self-sufficiency at the end of hospitalization. Three hypotheses have been identified to meet this goal. The practical part describes the results of the used tools for a particular department. The research group...

Scientific computing is used frequently in an increasing number of disciplines to accelerate scientific discovery. Many such computing problems involve the numerical solution of partial differential equations (PDE). In this thesis we explore and develop methodology for high-performance implementations of PDE solvers for shared-memory multiprocessor architectures. We consider three realistic PDE settings: solution of the Maxwell equations in 3D using an unstructured grid and the method of conjugate gradients, solution of the Poisson equation in 3D using a geometric multigrid method, and solution of an advection equation in 2D using structured adaptive mesh refinement. We apply software optimization techniques to increase both parallel efficiency and the degree of data locality. In our evaluation we use several different shared-memory architectures ranging from symmetric multiprocessors and distributed shared-memory architectures to chip-multiprocessors. For distributed shared-memory systems we explore methods of data distribution to increase the amount of geographical locality. We evaluate automatic and transparent page migration based on runtime sampling, user-initiated page migration using a directive with an affinity-on-next-touch semantic, and algorithmic optimizations for page-placement policies. Our results show that page migration increases the amount of geographical locality and that the parallel overhead related to page migration can be amortized over the iterations needed to reach convergence. This is especially true for the affinity-on-next-touch methodology whereby page migration can be initiated at an early stage in the algorithms. We also develop and explore methodology for other forms of data locality and conclude that the effect on performance is significant and that this effect will increase for future shared-memory architectures. Our overall conclusion is that, if the involved locality issues are addressed, the shared-memory programming model provides an efficient and productive environment for solving many important PDE problems.

L'objectif de ce travail de thèse a été d'évaluer, à partir d'outils de caractérisation électrique (spectroscopie d'impédance basse fréquence et courants thermo-stimulés), l'impact des étapes de polissage mécanochimique (CMP) et de recuits thermiques sur les propriétés diélectriques de matériaux utilisés pour les dernières générations de circuits intégrés. Une première partie est focalisée sur le matériau SiOCH poreux déposé par voie chimique « en phase vapeur » assisté par plasma (PECVD) suivant une approche porogène (p=26%, d=2nm et er=2,5). Son intégration dans les technologies 45nm nécessite l'utilisation d'un procédé de ‘CMP directe' qui induit une dégradation des propriétés isolantes attribuée à l'adsorption de surfactants et de molécules d'eau. L'analyse diélectrique sur une large gamme de fréquence (10-1Hz- 105Hz) et de température (-120°C -200°C) a mis en évidence plusieurs mécanismes de relaxation diélectrique et de conduction liés à la présence de molécules nanoconfinées (eau et porogène) dans les pores du matériau. L'étude de ces mécanismes a permis d'illustrer le phénomène de reprise en eau du SiOCH poreux ainsi que d'évaluer la capacité de traitements thermiques à en restaurer les performances. Une seconde partie concerne l'étude d'une résine époxy chargée avec des nanoparticules de silice, utilisée en tant que ‘wafer level underfill' dans les technologies d'intégration 3D. Les analyses en spectroscopie d'impédance ont montré que l'ajout de nanoparticules de silice s'accompagne d'une élévation de la température de transition vitreuse et de la permittivité diélectrique, ainsi que d'une diminution de la conductivité basse fréquence. L'autre contribution majeure des mesures diélectriques a été de montrer qu'un refroidissement trop rapide de la résine à l'issue de la réticulation était responsable d'une contrainte interne qui pourra occasionner des problèmes de fiabilité pour l'application. / The aim of the thesis was to investigate, by electrical means (dielectric spectroscopy and thermally stimulated current), the impact of the chemical-mechanical polishing process and of thermal treatments on the dielectric properties of materials used in state-of-the-art Integrated Circuit (IC) technologies. A first part focuses on the nanoporous SiOCH (p=26%, e=2 nm and er=2,5) thin films deposited by plasma enhanced chemical vapor deposition (PECVD) using a porogen approach. After undergoing a process of direct CMP for its integration in the 45 nm node technology and beyond, those films experience a degradation of the insulating properties due to the adsorption of water and surfactants. A dielectric analysis performed on a wide range of frequency (10-1Hz - 105Hz) and temperature (-120°C - 200°C) exhibited many dielectric relaxation and conduction mechanisms due to molecules (water and porogen) nano-confined in pores. The phenomenon of water uptake of the porous SiOCH has been enlightened and the efficiency of thermal treatment to restore its performances has been evaluated through the study of these mechanisms. A second part deals with an epoxy resin filled with nano-particles of silica used as ‘wafer level underfill' for the 3D integration. Impedance spectroscopy showed that the addition of nano-particles induces an increase in the glass transition temperature and dielectric permittivity, as well as a decrease of the low frequencyconductivity. Furthermore, the dielectric measurements showed that a fast cool down of the resin after the cross-linking stage give rise to internal stresses which could potentially lead to reliability issues.

Studie av kommunikation i projekt och identifikation av konflikterna som står som hinder för projektet.. Den studien består av olika tester, en intervju och en webbsida. Dessa metoder är lämpliga för just det studerade projektets situation och struktur och kan testa olika vinklar i kommunikationen. Fokusområden är: - Kvalitet - Struktur Utgående från den ovannämnda faktorerna har jag med hjälp av projektägaren och projektledaren gjort en del antaganden som berör kommunikationen i projektet och därefter har jag använt olika metoder för att testa dem. Svaren som jag fick utav dessa tester gav en bild om validiteten och de följande testerna har varit kompletterande till de föregående. / Study of communication in the project and identification of conflicts that stand in opposition to the project .. The study consists of various tests, an interview and a Web page. These methods are appropriate for the studied project situation and structure and can test different angles in communication. Focus areas are: - Quality - Structure Based on the above factors, I have with the help of the project owner and the project manager made ​​some assumptions that affect communication in the project and then I have used various methods to test them. The answers that I got out of these reviews gave a picture of the validity and how the following tests were complementary to the previous ones. / r.delemi@hotmai.com

This thesis examines the ways that fluctuations in voter expectations for the state of the economy affect party strategies, throughout 28 countries across the EU and OECD between 1995 and 2021. I thus make a theoretical contribution to the existing research by testing the theoretical models that claim that parties primarily respond to voter preferences and perceptions when conducting their policy strategies. Utilizing data from the Comparative Manifestos Project, the Eurobarometer, QOG and ParlGov, the study examines policy positions on economic issues, as presented in party manifestos ahead of elections. Using fixed-effects regressions with interaction variables, the effects of voter expectations on policy stances are examined, both in parliaments more generally as well as for each party family respectively. Specifically, Social-democratic, conservative, populist, Christian-democratic, and liberal parties are considered. Results show that when citizen expectations for the state of the economy worsen, parties show tendencies of shifting their policy stances to the left across the left-right scale. This is true across parliaments more generally, and results indicate that it may also be true when looking at each party family respectively. Most notably, results show that economic expectations impact the policy positions of parties even when controlling for the actual state of the economy, implying that parties are responsive to voter expectations independently of other macroeconomic considerations.

Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traffic representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-off study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

En la presente tesis doctoral se realiza un estudio detallado sobre el mecanismo de la reacción de reducción de oxígeno (ORR) en electrodos monocristalinos de platino. Para ello, se han realizado medidas electroquímicas usando la configuración de electrodo rotatorio de menisco colgante (HMRDE) con superficies con distinta estructura superficial y variando condiciones de la disolución de trabajo como el pH, fuerza iónica o la ausencia o presencia de bromuros. La conclusión principal que se extra de estos experimentos es la posibilidad de la existencia de un punto de bifurcación en el mecanismo, implicando el intermedio OOH, antes de la formación de peróxido de hidrógeno. Además, también se estudia la ORR y la reacción de oxidación de ácido fórmico en electrodos monocristalinos de Pt en presencia de acetonitrilo, como estudio previo al estudio de estas reacciones en disolventes orgánicos con pequeñas cantidades de agua. Por último, se estudia la ORR en un Aza-CMP, lo cual permite obtener información fundamental que se puede aplicar en estudios sobre el mecanismo de la ORR en los sitios activos de materiales de carbón funcionalizados con nitrógeno.