Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

Les anticorps à réactivité croisée sont caractérisés par leur capacité à reconnaitre des épitopes différents de ceux qui ont causé leur induction. Cela se produit lorsque des similitudes structurales entre les deux déterminants antigéniques deviennent suffisantes pour permettre une liaison spécifique. Nous rapportons ici pour la première fois la présence, à une haute fréquence, d'anticorps dans des échantillons de sang provenant de sujets vivant en France avec une protéine de Trypanosoma cruzi. Nous avons appelé ces anticorps ''Trypanosoma cruzi Cross-reactive antibodies'' ou TcCRA. Nos résultats montrent une forte séroprévalence des anticorps à réaction croisée, suggérant qu'ils sont induits par un immunogène largement répandu, acquis dès l’enfance et qui ne semble pas être associé à des agents pathogènes communs en clinique humaine. Les recherches effectuées in silico orientent vers un virus de la famille des Herpesviridae. Cette hypothèse est renforcée par la documentation d’un profil sérologique de séroconversion chez un patient qui a subi une transplantation de cellules souches allogéniques. Ce premier travail va servir de base à la mise en oeuvre d’investigations cliniques rétrospectives et prospectives destinées à élucider l’étiologie et l’importance clinique du biomarqueur TcCRA / Cross-reactive antibodies are characterized by their recognition of antigens that are different from the trigger immunogen. This happens when the similarity between two different antigenic determinants becomes adequate enough to enable a specific binding. Here, we report for the first time the presence, at an ‘‘abnormal’’ high frequency in blood samples from French human subjects, of antibodies that cross-react with a protein of Trypanosoma cruzi. We called these antibodies ‘‘Trypanosoma cruzi Cross-Reactive Antibodies’’ or TcCRA. Our findings show a large seroprevalence of cross-reactive antibodies and suggest that they are induced by a widely spread immunogen, acquired during childhood. Furthermore TcCRA serology does not seem to be associated with commonly known pathogens in clinical routine. Our hypothesis of the implication of a viral agent in the induction of TcCRA was further put forward when we documented a seroconversion pattern in a patient after allogenic stem cell transplantation. This initial exploratory work will serve as the basis for organizing prospective and retrospective clinical investigations, where we will pursue the analysis of TcCRA in order to elucidate its etiology and clinical importance

Les infections virales en particulier celles dues aux virus de la famille des Herpesviridae pendant la période d’aplasie et de lymphopénie à la suite d’une greffe de cellules souches hématopoïétiques (GCSH) peuvent occasionner des complications très graves, souvent associées à une morbidité et mortalité élevées. Les recommandations cliniques actuelles préconisent l’utilisation des antiviraux pour la prévention de certaines de ces infections. L’efficacité du famciclovir et de l’acyclovir contre les virus de l’herpès simplex (HSV), le virus varicella-zoster (VZV) et l’herpésvirus humain de type 6 (HHV-6) est bien reconnue, cependant il nous manque des données quant à leur effet contre le virus Epstein-Barr (EBV) et le cytomégalovirus (CMV) dans la population pédiatrique. L’objectif principal de ce projet de maitrise a été de mesurer l’incidence de l’infection aux virus HSV, VZV, EBV, CMV et HHV-6 et de mesurer l’association entre l’utilisation de la prophylaxie antivirale (acyclovir et famciclovir) et l’infection (virémie asymptomatique et maladie) avec le CMV et l’EBV dans une cohorte pédiatrique de GCSH allogéniques. Les données d'une cohorte de sujets ayant subis pour la première fois une GCSH enrôlés dans quatre centres de greffes pédiatriques au Canada entre juillet 2013 et mars 2017 (Étude TREASuRE) ont été utilisées. Le recrutement a été effectué au : CHU Sainte-Justine (Montréal) (n=86), British Columbia Children’s Hospital (Vancouver) (n=31), Winnipeg Children's Hospital and CancerCare Manitoba (n=28) et Alberta Children’s Hospital (n=11). Le suivi des patients avait débuté 1 mois avant la greffe et avait duré 13 mois. L’âge médian des patients au recrutement était de 6,3 ans. Les courbes de Kaplan-Meier ont permis d’estimer l'incidence cumulée des infections CMV et EBV avec intervalle de confiance (IC) à 95% à 100 jours post-greffe en fonction de la prophylaxie antivirale (acyclovir ou famciclovir). Les modèles multivariés de régression de Cox à risques proportionnels ont permis de mesurer l'association entre la prise d’antiviraux (acyclovir ou famciclovir) et le développement de ces infections. L’étude a inclus 156 sujets âgés de 0 à 21 ans. Les incidences cumulées de la virémie des virus de HSV, VZV, EBV, CMV et HHV-6 à 100 jours de suivi ont été respectivement de 2.5% (IC 95% : 0.8–7.6), 0.8% (IC 95% : 0.1–6.1), 34.5% (IC 95% : 27.6–42.6), 19.9% (IC 95% : 14.5-27.1) et 3.4% (IC 95% : 1.2–9.1). Les incidences cumulées pour CMV et EBV n’ont pas montré de différence statistiquement significative entre les groupes ayant reçu la prophylaxie antivirale (acyclovir ou famciclovir) et ceux qui ne l’ont pas reçu. Les analyses de Cox n’ont montré aucun effet significatif des antiviraux sur le CMV avec un HR ajusté de 0.55 (IC 95% : 0.24–1.26) pour l’acyclovir et de 0.82 (IC 95% : 0.30–2.29) pour le famciclovir. Il en était de même pour l’EBV avec un HR ajusté de 1.41 (IC 95% : 0.63–3.14) pour l’acyclovir et de 0.79 (IC 95% : 0.36–1.72) pour le famciclovir. Notre étude n’a montré aucune preuve d’effet de la prophylaxie antivirale avec le famciclovir et l’acyclovir contre l’EBV et le CMV. Très peu de cas de HSV et de VZV ont été diagnostiqués dans cette cohorte ce qui est conforme avec l’idée selon laquelle l’acyclovir et le famciclovir sont efficaces pour ces virus. / Viral infections, especially those involving members of the Herpesviridae during the period of aplasia and lymphopenia following allogeneic hematopoietic stem cell transplantation (HSCT), cause very serious complications, often associated with high morbidity and mortality. Current clinical guidelines recommend prophylactic use of antivirals, which has proven to be effective against certain viruses. The efficacy of famciclovir and acyclovir against herpes simplex viruses (HSV), varicella zoster virus (VZV) and human herpesvirus type 6 (HHV-6) is well-recognized, however, we lack data on their effects against Epstein-Barr virus (EBV) and cytomegalovirus (CMV) in the pediatric population. The main objective of this master's project was to measure the incidence of herpes virus infection, specifically by HSV, VZV, EBV, CMV and HHV-6, and to measure the association between the use of antiviral prophylaxis (acyclovir and famciclovir) and infection (including both asymptomatic viremia and disease) by CMV and EBV in a pediatric cohort of allogeneic HSCT. We used data from the TREASuRE cohort, which includes patients enrolled for a first allogeneic HSCT in four pediatric centers in Canada between July 2013 and March 2017. Recruitment was carried out at: CHU Sainte-Justine (Montreal) (n = 86), British Columbia Children's Hospital (Vancouver) (n = 31), Winnipeg Children's Hospital and CancerCare Manitoba (n = 28) and Alberta Children's Hospital (n = 11). Patient follow-up began 1 month before transplant and lasted 13 months. Median patient age at recruitment was 6.3 years. Kaplan-Meier curves were used to estimate the cumulative incidence of CMV and EBV infections with 95% confidence interval (CI) at 100 days post-transplant according to antiviral prophylaxis (acyclovir or famciclovir). Multivariate proportional hazards Cox regression models were used to measure the association between antiviral use (acyclovir or famciclovir) and the detection of these infections. The study included 156 subjects aged 0 to 21 years. The cumulative incidences of viremia due to HSV, VZV, EBV, CMV and HHV-6 at day 100 of follow-up were respectively 2.5% (CI 95%: 0.8–7.6), 0.8% (CI 95%: 0.1-6.1), 34.5% (CI 95%: 27.6-42.6), 19.9% (CI 95%: 14.5-27.1) and 3.4% (95% CI: 1.2-9.1). The cumulative incidences for CMV and EBV did not show a statistically significant difference between the groups who received antiviral prophylaxis (acyclovir or famciclovir) and those who did not. Cox analyses showed no significant effect of antivirals on CMV with an adjusted HR of 0.55 (95% CI: 0.24–1.26) for acyclovir and 0.82 (95% CI: 0.30–2.29) for famciclovir. The same was true for EBV with an adjusted HR of 1.41 (95% CI: 0.63–3.14) for acyclovir and 0.79 (95% CI: 0.36–1.72) for famciclovir. Our study showed no evidence of an effect with use of famciclovir or acyclovir prophylaxis on EBV and CMV infections. Very few cases of HSV and VZV infections were diagnosed in this cohort, which is consistent with the idea that acyclovir and famciclovir are effective against the latter viruses.

Human cytomegalovirus (HCMV) is a widespread human herpesvirus pathogen and prototypical member of the β-herpesvirus subfamily. Like all herpesviruses, the virus establishes a lifelong latent infection following host exposure, which has the potential to reactivate periodically and contribute to recurrent disease processes. In individuals with weak or compromised immune systems, such reactivation can lead to profound pathology. Understanding how latent infections are maintained is important for uncovering how HCMV causes disease. The study of viral genes that are expressed during latent infection grants insight into how latency is regulated and how it could be therapeutically targeted. To that end, this project has sought to evaluate the functional significance of one such viral gene termed LUNA in the context of latency. In models of experimental latent infection based on primary myeloid cells, levels of viral gene transcription were found to be significantly reduced following infection with LUNA deletion mutant viruses, consistent with corresponding observable changes in post-translational histone modifications over the viral promoters of latency-associated genes. Additionally, using luciferase reporter systems, latency-associated viral gene promoters became activated in response to the expression of wild-type LUNA. Together, these findings argue for a role of LUNA in regulating viral gene expression during latent HCMV infection. One possible mechanism by which LUNA may fulfil its role is by targeting cellular ND10 structures, known intrinsic inhibitors of herpesvirus gene expression, for disruption. In support of this, latently infected cells were found to be devoid of ND10, a phenotype that was recapitulated by the direct expression of wild-type LUNA. Furthermore, mutation studies confirmed the identification of a novel deSUMOylase activity encoded by LUNA that was responsible for mediating ND10 disruption. Use of a catalytically inactive LUNA mutant in transcriptional analyses of latent infection also generated similar results as with the LUNA deletion viruses. Overall, these data support the hypothesis that LUNA serves as an important regulator of viral gene expression during latency, which is likely linked to its ability to target ND10 structures for disruption, thus raising the possibility that inhibition of deSUMOylation may serve as a novel therapeutic strategy to target latent HCMV infection.

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.