No description available.

For the future of sustainable energy, renewable energy will need to significantly penetrate existing utility grids. While various renewable energy sources are networked with high-voltage DC grids, integration between these high-voltage DC grids and the existing AC grids is a significant technical challenge. Among the limited choices available, the modular multi-level converter (MMC) is the most prominent interface converter used between the DC and AC grids. This subject has been widely pursued in recent years. One of the important design challenges when using an MMC is to reduce the capacitor size associated with each module. Currently, a rather large capacitor bank is required to store a certain amount of line-frequency related circulating energy. Several control strategies have been introduced to reduce the capacitor voltage ripples by injecting certain harmonic current. Most of these strategies were developed using trial and error and there is a lack of a systematic means to address this issue. Most recently, Yadong Lyu has proposed to control the modulation index in order to reduce capacitor ripples. The total elimination of the unwanted circulating power associated with both the fundamental line frequency and the second-order harmonic was demonstrated, and this resulted in a dramatic reduction in capacitor size. To gain a better understanding of the intricate operation of the MMC, this thesis proposes a state-space analysis technique in the present paper. Combining the power flow analysis with the state trajectory portrayed on a set of two-dimensional state plans, it clearly delineates the desired power transfer from the unwanted circulating energy, thus leading to an ultimate reduction in the circulation energy and therefore the required capacitor volume. / Master of Science

Power systems are protected by numerical relays that detect and isolate faults that may occur on power systems. The correct operation of the relay is very important to maintain the security of the power system. <p>Numerical relays that use voltage measurements from the power system provided by coupling capacitor voltage transformers (CCVT) have sometimes difficulty in correctly identifying a fault in the protected area. The fundamental frequency voltage phasor resulting from these CCVT measurements may result in a deviation from the true value and therefore may locate this phasor temporarily in the incorrect operating region. This phasor deviation is due to the CCVT behavior and the CCVT introduces spurious decaying and oscillating transient signal components on top of the original voltage received from the power system in response to sudden voltage changes produced during faults. Most of the existing methods for estimating the voltage phasor do not take advantage of the knowledge of the CCVT behavior that can be obtained from its design parameters.<p>A new least squares error method for phasor estimation is presented in this thesis, which improves the accuracy and speed of convergence of the phasors obtained, using the knowledge of the CCVT behavior. The characteristics of the transient signal components introduced by the CCVT, such as frequencies and time constants of decay, are included in the description of the curve to be fitted, which is required in a least squares fitting technique. Parameters such as window size and sampling rate for optimum results are discussed.<p>The method proposed is evaluated using typical power systems, with results that can be compared to the response if an ideal potential transformer (PT) were used instead of a CCVT. The limitations of this method are found in some specific power system scenarios, where the natural frequencies of the power system are close to that of the CCVT, but with longer time constants. The accuracy with which the CCVT parameters are known is also assessed, with results that show little impact compared to the improvements achievable.

Power systems are protected by numerical relays that detect and isolate faults that may occur on power systems. The correct operation of the relay is very important to maintain the security of the power system. <p>Numerical relays that use voltage measurements from the power system provided by coupling capacitor voltage transformers (CCVT) have sometimes difficulty in correctly identifying a fault in the protected area. The fundamental frequency voltage phasor resulting from these CCVT measurements may result in a deviation from the true value and therefore may locate this phasor temporarily in the incorrect operating region. This phasor deviation is due to the CCVT behavior and the CCVT introduces spurious decaying and oscillating transient signal components on top of the original voltage received from the power system in response to sudden voltage changes produced during faults. Most of the existing methods for estimating the voltage phasor do not take advantage of the knowledge of the CCVT behavior that can be obtained from its design parameters.<p>A new least squares error method for phasor estimation is presented in this thesis, which improves the accuracy and speed of convergence of the phasors obtained, using the knowledge of the CCVT behavior. The characteristics of the transient signal components introduced by the CCVT, such as frequencies and time constants of decay, are included in the description of the curve to be fitted, which is required in a least squares fitting technique. Parameters such as window size and sampling rate for optimum results are discussed.<p>The method proposed is evaluated using typical power systems, with results that can be compared to the response if an ideal potential transformer (PT) were used instead of a CCVT. The limitations of this method are found in some specific power system scenarios, where the natural frequencies of the power system are close to that of the CCVT, but with longer time constants. The accuracy with which the CCVT parameters are known is also assessed, with results that show little impact compared to the improvements achievable.

Le convertisseur multiniveau modulaire (MMC) est une solution appropriée pour les réseaux HVDC grâce à sa modularité, sa faible fréquence de commutation et sa tension alternative quasi-sinusoïdale. En raison de sa topologie, son modèle mathématique est assez complexe et est donc souvent simplifié au stade de la conception. En particulier, la résistance équivalente au bras R, l'inductance du bras L et le courant circulant sont souvent négligés. Toutefois, les résultats expérimentaux obtenus avec notre prototype monophasé de MMC à pont complet à six niveaux ont montré que ces hypothèses ne sont pas toujours acceptables. Dans ce contexte, l'objectif de cette thèse est d'étudier l'impact de R, L et du courant de circulation sur la tension du condensateur du module et sur la zone de fonctionnement du MMC. Premièrement, nous avons étendu le modèle basé sur les intégrales communément utilisé et nous avons clarifié les hypothèses sur lesquelles il repose. Entre autres, des expressions pour les courants de circulation et courant DC ont été développées et comparées à celles que l’on trouve dans la littérature. Cela nous a permis d'analyser l'ondulation de la tension du condensateur du module en fonction de R et L, sans courant de circulation. Deuxièmement, pour surmonter les limites du modèle basé sur l'intégrale, nous avons proposé d'utiliser un modèle MMC invariant dans le temps en régime permanent dans le système dq0. Quelques hypothèses seulement sont nécessaires pour obtenir ce modèle, mais une évaluation numérique est requise. Cela nous a permis d'analyser la tension moyenne du condensateur du module et l'ondulation de tension du condensateur du module en fonction de R et L, avec et sans courant de circulation. Troisièmement, en utilisant le modèle invariant dans le temps en régime permanent, nous avons développé un diagramme PQ détaillé du MMC. Outre la limite de courant AC, la limite de courant DC et la limite d'indice de modulation classiques, nous avons ajouté plusieurs limites internes: courant de l'IGBT, courant efficace des bras et ondulation du courant et de la tension du condensateur du module. Les résultats ont été confirmés par simulation numérique à l'aide d'un modèle détaillé Matlab Simulink SimPowerSystems. Les résultats présentés dans cette thèse pourraient être utilisés pour optimiser le dimensionnement des composants de la MMC en fonction de sa zone d’exploitation et pour évaluer l’impact de différents paramètres sur les performances du MMC. / The modular multilevel converter is a suitable solution for HVDC grids thanks to its modularity, low switching frequency and quasi-sinusoidal AC voltage. However, due to its topology, its mathematical model is quite complex and is therefore often simplified at the design stage. In particular, the arm equivalent resistance R, the arm inductance L and the circulating current are often neglected. But experimental results obtained with our 1-ph 6-level full-bridge MMC prototype showed that these hypotheses are not always acceptable. In this context, the goal of this thesis is to study the impact of accounting for R, L and the circulating current on the module capacitor voltage and on the operating area of the converter. First, we extended the commonly used integral based model and we clarified the hypotheses behind it. Among others, expressions for the circulating and dc currents have been developed and compared with the one that can be found in the literature. It allowed us to analyze the module capacitor voltage ripple as a function of R and L, without circulating current only. Second, to overcome the limitations of the integral based model, we proposed to use a steady state time invariant (DeltaSiga) MMC model in dq0 frame. Only few hypotheses are required to obtain this model, but a numerical evaluation is required. It allowed us to analyze the module capacitor average voltage and the module capacitor voltage ripple as a function of R and L, with and without circulating current. Third, using the steady state time invariant model, we developed a detailed PQ diagram of the MMC. In addition to the conventional AC current limit, DC current limit and modulation index limit, we added several internal limits: IGBT current, arm rms current and module capacitor voltage and current ripple. The results have been confirmed by numerical simulation using a detailed Matlab Simulink SimPowerSystems model. The results presented in this thesis could be used to optimize the sizing of the components of the MMC considering its operating area, and to assess the impact of different parameters on the MMC performance.

No description available.

Submitted by Lucienne Costa (lucienneferreira@ufcg.edu.br) on 2017-12-13T16:54:10Z No. of bitstreams: 1 CÉLIO ANÉSIO DA SILVA - TESE (PPGEE) 2014.pdf: 1651226 bytes, checksum: a70dc4864a551f419c02ff41303eaffc (MD5) / Made available in DSpace on 2017-12-13T16:54:11Z (GMT). No. of bitstreams: 1 CÉLIO ANÉSIO DA SILVA - TESE (PPGEE) 2014.pdf: 1651226 bytes, checksum: a70dc4864a551f419c02ff41303eaffc (MD5) Previous issue date: 2014-05-29 / Capes / Um novo método de obtenção de parâmetros de filtros digitais recursivos (FDR) é apresentado para reduzir o impacto da resposta transitória dos Transformadores de Potencial Capacitivos (TPC) sobre o desempenho dos sistemas de medição, proteção e controle. Assumindo uma topologia predefinida, os parâmetros dos filtros são obtidos a partir da resposta em frequência do TPC de interesse. Diferentemente das técnicas reportadas na literatura, o método se aplica com facilidade a TPC de diferentes classes de tensão e independe das características operacionais do sistema. Para tanto, faz-se necessário conhecer a resposta em frequência do TPC em questão, no espectro de frequência de interesse. A validação do método é realizada através de simulações digitais em tempo real via simulador RTDSTM (Real Time Digital Simulator). As análises são baseadas em dados de sistemas elétricos reais e no funcionamento dinâmico dos filtros através da estimação dos fasores das tensões e estudos de localização de falta. A partir dos resultados obtidos, verifica-se que a presença dos FDR reduz significativamente os erros de medição causados pelos TPC quando submetidos a condições transitórias. Portanto, os FDR surgem como uma forma simples e de baixo custo para melhorar o desempenho e a confiabilidade dos sistemas de medição, proteção e controle. / A new method for obtaining recursive digital filter (FDR) parameters is presented in order to reduce the impact of Coupling Capacitor Voltage Transformer (CCVT) transient response on the performance of the measurement, protection and control systems. Assuming a pre-defined topology, the filter parameters are obtained from the CCVT frequency response of interest. Unlike the techniques reported in the literature, the method applies easily to CCVT of different voltage classes and it does not depend on the operating characteristics of the system, therefore, it is necessary to know the frequency response of the CCVT on the frequency spectrum of interest. The method is validated is through digital simulation using the RTDSTM (Real Time Digital Simulator). The analyzes are based on data obtained from electrical systems in service and on the dynamic performance of the filters by estimating the phasors of voltages and fault location studies. It is shown that the presence of FDR significantly reduces measurement errors caused by CCVT when subjected to transient conditions, therefore, the FDR arises as a simple and low cost alternative to improve the performance and reliability of measurement systems, protection and control.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

This thesis provides insight into state-of-the-art Modular Multilevel Converters (MMC) for medium and high voltage applications. Modular Multilevel Converters have increased in interest in many industrial applications, as they offer the following advantages: modularity, scalability, reliability, distributed location of capacitors, etc. In this study, the modeling, control and design considerations of modular based multilevel converters, with an emphasis on the reliability of the converter, is carried out. Both modular multilevel converters with half-bridge and full-bridge sub-modules are evaluated in order to provide a complete analysis of the converter. From among the family of modular based hybrid multilevel converters, the newly released Alternate Arm Converter (AAC) is considered for further assessment in this study. Thus, the modular multilevel converter with half-bridge and full-bridge power cells and the Alternate Arm Converter as a commercialized hybrid structure of this family are the main areas of study in this thesis. Finally, the DC fault analysis as one of the main issues related to conventional VSC converters is assessed for Modular Multilevel Converters (MMC) and the DC fault ride-through capability and DC fault current blocking ability is illustrated in both the Modular Multilevel Converter with Full-Bridge (FB) power cells and in the Alternate Arm Converter (AAC). Accordingly, the DC fault control scheme employed in the converter and the operation of the converter under the fault control scheme are explained. The main contributions of this study are as follows: The new D-Q model for the MMC is proposed for use in the design of the inner and outer loop control. The extended control scheme from the modular multilevel converter is employed to control the Alternate Arm Converters. A practical reliability-oriented sub-module capacitor bank design is described based on different reliability modeling tools. A Zero Current Switching (ZCS) scheme of the Alternate Arm Converter is presented in order to reduce the switching losses of the Director Switches (DS) and, accordingly, to implement the ZCS, a design procedure for the Arm inductor in the AAC is proposed. The capacitor voltage waveform is extracted analytically in different load power factors and the waveforms are verified by simulation results. A reliability-oriented switching frequency analysis for the modular multilevel converters is carried out to evaluate the effect of the switching frequency on the MMC's operation. For the latter, a DC fault analysis for the MMC with Full-Bridge (FB) power cells and the AAC is performed and a DC fault control scheme is employed to provide the capacitor voltage control and DC fault current limit, and is illustrated herein. / Master of Science

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.