The classical capacitance voltage characteristics based on the depletion approximation, is adequate at reverse bias, but introduces errors at high forward bias. Because of its inherent simplicity and compactness this classical depletion model is well studied and widely used in circuit simulators. In this work, a new model for the semiconductor space charge region (SCR) capacitance, based on physical justification, will be derived. This new model takes three input parameters, C0 , Vbi and m, thus eliminating the fitting parameter FC currently used in SPICE. This new model is applicable for any applied voltage and will be compared with the SCR capacitance extracted from the numerical device simulator PISCES, and with the SCR capacitance models proposed by Gummel and Poon and by DeGraaff and Klaassen.

This thesis explores high voltage converter circuits for MEMS applications using micromachined devices. A novel MEMS based tunable DC-DC converter has been developed. Conventional high voltage converters based on charge pumps are unable to convert voltages to higher than few tens of volts due to power handling limitations of the CMOS components. In order to overcome this limitation a high voltage circuit has been proposed, which when integrated with micromachined switches will generate output voltages in the range of 100 Volts. The converter is based on a two phase switched capacitor circuit, and allows regulation of voltage conversion ratio. Three prototype circuits have been built for proof of concept. A test program has been written for synchronized CPLD based control of the switched capacitors. Individual capacitor fabrication technology is explored using two methods - Porous Silicon and DRIE processing. A micromachined capacitor bank has also been fabricated in silicon using a novel process sequence which provides for critical real estate savings and integration benefits. It enables on-chip integration of numerous microcapacitors, without losing customized configurability of the capacitor bank. The technique utilizes polyimide to facilitate lithography on a highly contoured surface. Plain capacitors have been fabricated on silicon with oxide-nitride-oxide stack being used as the dielectric to provide a building block for further fabrication of a variety of capacitors.

This thesis concentrates on RF/microwave characterization and modeling of planar spiral inductors and pad stack parasitics. The inductors varied in size from 1.9 to 15.3 nH. Several approaches were examined for modeling the planar spiral inductors. The approach developed herein is built around an existing composite model (available in commercial computer-aided design software), with added series and shunt impedances at both the input and output of the existing composite model. Artificial neural network (ANN) software was used to determine the correction impedance values. Another approach investigated was to model the S-parameters of the inductor using a space- mapping model of the input parameters for the existing model. The correction impedance modeling approach was theoretically sound but the level of accuracy need for the ANN model was not obtainable. The space mapping approach had merit but a substrate and parameter scalable model could not be achieved. A pad stack is a section of microstrip line that a surface mounted element is affixed to; these pad stacks are standardized for specific element sizes, so for example any 0805 (80 mils by 50 mils) element may have the same pad stack whether it is a capacitor, inductor or resistor. The pad stack models were necessary because a capacitor model originally developed at the University of South Florida did not include parasitic effects for different input connections. The pad stack parasitic models can be broken down into three types: dual-input, tri-input, and quad-input. Each of the dual- and tri- input models have input angles of either 0 degrees, 45 degrees, or 90 degrees. The models were developed using a combination of microstrip and lumped elements.

The performances of current electrical energy storage systems (both batteries and electrochemical capacitors) are not capable of meeting the ever-increasing demands of emerging technologies. This is because batteries often suffer from slow power delivery, limited life-time, and long charging time whereas electrochemical capacitors suffer from low energy density. While extensive efforts have been made to the development of novel electrode materials, progress has been hindered by the lack of a profound understanding on the complex charge storage mechanism. Therefore, the main objective of this research is to develop novel electrode materials which can exhibit both high energy and power density with prolonged life-time and to gain a fundamental understanding of their charge storage mechanism. First, nanostructured, thin, and conformal coatings of transition metal oxides have been deposited onto three-dimensional porous substrates of current collectors to form composite electrodes. The structures and compositions of the oxide coatings are further altered by a controlled annealing process and characterized by electron microscopy and spectroscopy, laboratory X-ray diffraction, gas adsorption analysis, and in-situ and ex-situ synchrotron-enabled X-ray diffraction and absorption spectroscopy. The structural features have also been correlated with the electrochemical behavior of the transition metal oxides as an electrode in an electrochemical capacitor. It is found that the electrochemical performance of the composite electrodes depends sensitively on the composition, nanostructure, and morphology of the oxide coatings. When optimized, the electrodes displayed the highest energy and power density with excellent cycling life among all materials reported for electrochemical capacitors. Finally, new charge storage mechanisms have also been proposed for the novel electrode materials based on insights gained from in-situ synchrotron-based X-ray absorption spectroscopy.

Electrostatically actuated parallel-plate MEMS tunable capacitors are desired elements for different applications including sensing, actuating and communications and RF (radio frequency) engineering for their superior characteristics such as quick response, high Q-factor and small size. However, due to the nature of their coupled electrostatic-structural physics, they suffer from low tuning range of 50% and have nonlinear capacitance-voltage (C-V) responses which are very sensitive to the voltage change near pull-in voltage. Numerous studies in the literature introduce new designs with high tunability ranging from 100% to over 1500%, but improvement of the nonlinearity and high sensitivity of the capacitor response have not received enough attention. In this thesis, novel highly tunable capacitors with high linearity are proposed to reduce sensitivity to the voltage changes near pull-in. The characteristic equations of a perfectly linear capacitor are first derived for two- and three-plate capacitors to obtain insight for developing linear capacitance-voltage responses. The devices proposed in this research may be classified into three categories: designs with nonlinear structural rigidities, geometric modifications and flexible moving electrodes. The concept of nonlinear supporting beams is exploited to develop parallel-plate capacitors with partially linear C-V curves. Novel electrodes with triangular, trapezoidal, butterfly, zigzag and fishbone shapes and structural/geometric nonlinearities are used to increase the linearity and tuning ratio of the response. To investigate the capacitors' behavior, an analytical approximate model is developed which can drastically decrease the computation time. The model is ideal for early design and optimization stages. Using this model, design variables are optimized for maximum linearity of the C-V responses. The results of the proposed modeling approach are verified by ANSYS FEM simulations and/or experimental data. When the fabrication process has dimensional limitations, design modifications and geometric enhancements are implemented to improve the linearity of the C-V response. The design techniques proposed in this thesis can provide tunabilities ranging from 80% to over 350% with highly linear regions in resulting C-V curves. Due to the low sensitivity of the capacitance to voltage changes in new designs, the entire tuning range is usable. Furthermore, the effect of fabrication uncertainties on parallel-plate capacitors performance is studied and a sensitivity analysis is performed to find the design variables with maximum impact on the C-V curves. An optimization method is then introduced to immunize the design against fabrication uncertainties and to maximize the production yield for MEMS tunable capacitors. The method approximates the feasible region and the probability distribution functions of the design variables to directly maximize the yield. Numerical examples with two different sets of design variables demonstrate significant increase in the yield. The presented optimization method can be advantageously utilized in design stage to improve the yield without increasing the fabrication cost or complexity.

Electrostatically actuated parallel-plate MEMS tunable capacitors are desired elements for different applications including sensing, actuating and communications and RF (radio frequency) engineering for their superior characteristics such as quick response, high Q-factor and small size. However, due to the nature of their coupled electrostatic-structural physics, they suffer from low tuning range of 50% and have nonlinear capacitance-voltage (C-V) responses which are very sensitive to the voltage change near pull-in voltage. Numerous studies in the literature introduce new designs with high tunability ranging from 100% to over 1500%, but improvement of the nonlinearity and high sensitivity of the capacitor response have not received enough attention. In this thesis, novel highly tunable capacitors with high linearity are proposed to reduce sensitivity to the voltage changes near pull-in. The characteristic equations of a perfectly linear capacitor are first derived for two- and three-plate capacitors to obtain insight for developing linear capacitance-voltage responses. The devices proposed in this research may be classified into three categories: designs with nonlinear structural rigidities, geometric modifications and flexible moving electrodes. The concept of nonlinear supporting beams is exploited to develop parallel-plate capacitors with partially linear C-V curves. Novel electrodes with triangular, trapezoidal, butterfly, zigzag and fishbone shapes and structural/geometric nonlinearities are used to increase the linearity and tuning ratio of the response. To investigate the capacitors' behavior, an analytical approximate model is developed which can drastically decrease the computation time. The model is ideal for early design and optimization stages. Using this model, design variables are optimized for maximum linearity of the C-V responses. The results of the proposed modeling approach are verified by ANSYS FEM simulations and/or experimental data. When the fabrication process has dimensional limitations, design modifications and geometric enhancements are implemented to improve the linearity of the C-V response. The design techniques proposed in this thesis can provide tunabilities ranging from 80% to over 350% with highly linear regions in resulting C-V curves. Due to the low sensitivity of the capacitance to voltage changes in new designs, the entire tuning range is usable. Furthermore, the effect of fabrication uncertainties on parallel-plate capacitors performance is studied and a sensitivity analysis is performed to find the design variables with maximum impact on the C-V curves. An optimization method is then introduced to immunize the design against fabrication uncertainties and to maximize the production yield for MEMS tunable capacitors. The method approximates the feasible region and the probability distribution functions of the design variables to directly maximize the yield. Numerical examples with two different sets of design variables demonstrate significant increase in the yield. The presented optimization method can be advantageously utilized in design stage to improve the yield without increasing the fabrication cost or complexity.

Well dispersed aqueous suspensions containing single-walled carbon nanotubes (SWCNTs) from bulk powders were prepared with surfactant and without surfactant by acid functionalization. SWCNT coated electrodes were then prepared from the SWCNT aqueous suspensions using various methods to create uniform nanoporous networks of SWCNTs on various substrates and stainless steel (SST) current collectors for use as ultracapacitor electrodes. Drop coating, high voltage electro-spraying (HVES), inkjet printing, and electrophoretic deposition (EPD) methods were evaluated. Optical and scanning electron microscope images were used to evaluate the SWCNT dispersion quality of the various electrodes. Ultimately an EPD process was established which reliably produced uniform SWCNT nanoporous networks on SST substrates. The prepared SWCNT coated electrodes were characterized using cyclic voltammetry and their capacitance was determined. A correlation between extended EPD processing times, EPD processing temperatures, and electrode capacitance was quantified. Optimum EPD processing occurs where linear capacitance gains were observed for processing times less than 10 minutes. At processing times between 10 – 60 minutes a non-linear relationship demonstrated diminishing capacitance gains with extended EPD processing times. Likewise, optimum EPD processing occurs when the processing temperature of the SWCNT suspension is raised above room temperature. At processing temperatures from 45°C to 60°C an increase in capacitance was observed over the room temperature (22°C) electrodes processed for the same durations. Conversely, for processing temperatures less than room temperature, at 5°C, a decrease in capacitance was observed. It was also observed that SWCNT electrodes processed at 60°C processing temperatures resulted in 4 times the capacitance of 5°C electrodes for the same processing times, when the durations were 8 minutes or less. For samples with raised processing temperatures the time dependent capacitance gains were observed to be significantly diminished beyond 10 minute processing times. The SWCNT network thickness was also correlated to EPD processing temperature and capacitance. A linear relationship was identified between the SWCNT network thickness and the capacitance of the electrode. It was also observed that elevated processing temperatures increase the EPD deposition rate of SWCNTs, produce thicker SWCNT networks, and thus create electrodes with higher capacitance than electrodes processed at lower EPD processing temperatures. EPD of SWCNTs was demonstrated in this work to be an effective method for the fabrication of SWCNT ultracapacitor electrodes. Characterization of the process determined that optimal EPD processing occurs within the first 10 minutes of processing time and that elevated processing temperatures yield higher SWCNT deposition rates and higher capacitance values. In this work the addition of SWCNT nanoporous networks to SST electrodes resulted in increases in capacitance of up to 398 times the capacitance of the uncoated SST electrodes yielding a single 1cm2 electrode with a capacitance of 91mF and representing an estimated specific capacitance for the processed SWCNT material of 45.78F/g.

As microprocessors move towards higher frequencies, lower operating voltages and higher power consumption, supplying noise-free power to the ICs becomes increasingly challenging. Decoupling capacitors with low inductance interconnections are critical to meet the power supply impedance targets. A variety of capacitors are used today to provide decoupling at different frequencies. Surface-mount multi-layer ceramic capacitors currently used at package level provide decoupling only till about 100 MHz because of the component and lead inductances. Embedding thin film capacitors into the package can expand the operating range of package level capacitors to low GHz frequencies. Thin films with capacitance of several microfarads and organic-compatible processes are required for embedding decoupling capacitors at package level. The organic-compatible high-permittivity materials available today do not provide adequate capacitance for the application on hand. While ferroelectric thin films can provide the required capacitance, processing temperatures over 300o C are required to achieve crystalline films with high permittivity. Hence, there is a need to develop novel materials and processes to integrate decoupling capacitors into currently prevalent organic packages. To this end, hydrothermal synthesis and sol-gel synthesis of BaTiO3 films were explored in this study. BaTiO3 films were synthesized by low temperature hydrothermal conversion of metallic titanium. Hydrothermal process parameters such as bath molarity and temperature were optimized to obtain thin films with grain sizes close to 100 nm, at temperatures less than 100o C. Novel post-hydrothermal treatments were developed to improve the dielectric properties of the films. Sol-gel process requires sintering at >700o C to obtain crystalline BaTiO3 films. However, the films can be synthesized on free-standing copper foils and subsequently integrated into organic packages using lamination. Prevention of foil oxidation during sintering is critical. Nickel and titanium barriers explored in this study were ineffective due to instabilities at the interfaces. Hence, films were synthesized on bare copper foils by controlling the oxygen partial pressure during sintering. Using these techniques BaTiO3 thin films with capacitances of 400 1000 nF/cm2 and breakdown voltages of 6 15 V were demonstrated. The films synthesized via either techniques exhibited stable dielectric properties up to 8 GHz owing to fine grain sizes.

Polymer/ceramic nanocomposites benefit by combining high permittivities (r) of metal oxide nanoparticles with high dielectric strength and excellent solution-processability of polymeric hosts. Simple mixing of nanoparticles and polymer generally results in poor quality materials due mainly to the agglomeration of nanoparticles and poor miscibility of nanoparticles in host materials. Surface modification of metal oxide nanoparticles with phosphonic acid-based ligands was found to afford a robust surface modification and improve the processablity and the quality of nanocomposites. The use of phosphonic-acid modified barium titanate (BaTiO₃) nanoparticles in dielectric nanocomposites dramatically improved the stability of the nanoparticle dispersion and the quality of the nanocomposites. Surface modification of BaTiO₃ nanoparticles allowed high quality nanocomposite thin films in ferroelectric polymer hosts such as poly(vinylidene fluoride-co-hexafluoropropylene) with large volume fractions (up to 50 vol. %), which exhibited a remarkable combination of a high permittvity (35 at 1 kHz) and a high breakdown strength (210 V/µm) leading to a maximum energy storage density of 6.1 J/cm³. The effect of nanoparticle volume fractions on the dielectric properties of this nanocomposite system was investigated and compared with theoretical models. At high volume fraction of nanoparticles, the porosity of the nanocomposites was found to have important role in the dielectric performance. A combined effective medium theory and finite difference simulation was used to model the dielectric properties of high volume fraction dielectric nanocomposites with porosity. These results provide a guideline to optimize the volume fractions of nanoparticles for maximum energy density. Nanocomposites based on phosphonic acid-modified BaTiO₃ nanoparticles can also be used as printable high permittivity dielectrics in organic electronics. High volume fractions (up to 37 vol. %) of phosphonic acid-modified BaTiO₃ nanoparticles dispersed in cross-linked poly(4-vinylphenol) allowed solution-processable high permittivity thin films with a large capacitance density (~50 nF/cm²) and a low leakage current (10 8 A/cm²) suitable as a gate insulator in organic field-effect transistors (OFETs). Pentacene-based OFETs using these nanocomposites showed a low threshold voltage (< -2.0 V) and a large on/off current ratio (Ion/off 104 ~ 106) due to the high capacitance density and low leakage current of the gate insulator.

Title from PDF of title page. / Document formatted into pages; contains 71 pages. / Thesis (M.S.E.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: This thesis concentrates on RF/microwave characterization and modeling of planar spiral inductors and pad stack parasitics. The inductors varied in size from 1.9 to 15.3 nH. Several approaches were examined for modeling the planar spiral inductors. The approach developed herein is built around an existing composite model (available in commercial computer-aided design software), with added series and shunt impedances at both the input and output of the existing composite model. Artificial neural network (ANN) software was used to determine the correction impedance values. Another approach investigated was to model the S-parameters of the inductor using a space- mapping model of the input parameters for the existing model. The correction impedance modeling approach was theoretically sound but the level of accuracy need for the ANN model was not obtainable. The space mapping approach had merit but a substrate and parameter scalable model could not be achieved. / ABSTRACT: A pad stack is a section of microstrip line that a surface mounted element is affixed to; these pad stacks are standardized for specific element sizes, so for example any 0805 (80 mils by 50 mils) element may have the same pad stack whether it is a capacitor, inductor or resistor. The pad stack models were necessary because a capacitor model originally developed at the University of South Florida did not include parasitic effects for different input connections. The pad stack parasitic models can be broken down into three types: dual-input, tri-input, and quad-input. Each of the dual- and tri- input models have input angles of either 0 degrees, 45 degrees, or 90 degrees. The models were developed using a combination of microstrip and lumped elements. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.