Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work.

Nesta dissertação é apresentada a aplicação da programação geométrica no projeto de uma fonte de tensão de referência de baixa tensão de alimentação que pode ser integrada em tecnologias padrões CMOS. Também são apresentados os resultados experimentais de um projeto da fonte de bandgap feito por um método de projeto convencional, cuja experiência motivou e ajudou ao desenvolvimento da formulação do programa geométrico proposta neste trabalho. O programa geométrico desenvolvido nesta dissertação otimiza o desempenho da fonte de bandgap e agiliza seu tempo de projeto. As expressões matemáticas que descrevem o funcionamento e as principais especificações da fonte de bandgap foram geradas e adaptadas ao formato de um programa geométrico. A compensação da temperatura, o PSRR, o consumo de corrente, a área, a tensão de saída e a sua variação por causa da tensão de offset do OTA, e a estabilidade são as principais especificações deste tipo de fonte de tensão de referência e fazem parte do programa geométrico apresentado neste trabalho. Um exemplo do projeto usando o programa geométrico formulado neste trabalho, mostra a possibilidade de projetar a fonte de bandgap em alguns minutos com erros baixos entre os resultados do programa geométrico e de simulação. / This work presents the application of geometric programming in the design of a CMOS low-voltage bandgap voltage reference source. Test results of a bandgap voltage reference designed via a conventional method are showed, this design experience motivated and helped to formulate the geometric program developed in this work. The geometric program developed in this work optimizes the bandgap source performance and speeds up the design time. The mathematical expressions that describe the bandgap source functioning and specifications were developed and adapted in the geometric program format. The temperature compensation, the PSRR, the current consumption, the area, the output voltage and its variations under the operational tranconductance amplifier offset voltage, and the stability are the main specifications of this type of bandgap reference source and they are included into the geometric program presented in this work. An example of the design using the geometric program formulated in this work, shows the possibility of designing the bandgap source in a few minutes with low errors between the geometric program results and the simulation results.

Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in typical applications. / Graduation date: 1992

The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic range RF front-ends. The contributions from this research are summarized as follows: 1. The first-ever comparison study and comprehensive analysis of small-signal linearity (IIP3) for npn and pnp SiGe HBTs on SOI. 2. A novel comparison of large-signal robustness of npn and pnp SiGe HBTs for use in high-performance RF front-ends. 3. A systematic and rigorous comparison of SiGe HBT compact models for high-fidelity distortion modeling. 4. The first-ever feasibility study of using weakly-saturated SiGe HBTs for use in severely power constrained RF front-ends. 5. A novel X-band Low Noise Amplifier (LNA) using weakly-saturated SiGe HBTs. 6. Design and comprehensive analysis of RF switches with enhanced large-signal linearity. 7. Development of novel methods to reduce crosstalk noise in mixed-signal circuits and the first-ever analysis of crosstalk noise across temperature. 8. Design of a very high-linearity cellular band quadrature modulator for use in base-station applications using first-generation complementary SiGe HBTs.

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies.

This thesis explores the critical advantages of using silicon-germanium (SiGe) HBTs for RF front-end design. The first chapter looks at the SiGe BiCMOS technology platform and its important performance metrics. The second chapter discusses ultra-wide tuneability and the critical role that this functionality can have on real world applications. The third chapter presents simulated and measured results of two wideband ring oscillators (8-18 GHz) designed and fabricated in the Jazz 120 BiCMOS platform. A 7-22 GHz wideband VGA in the 8HP platform is also presented further exemplifying the wideband capabilities of SiGe HBTs.

PCM test structures are commonly used to check the produced wafers from the standpoint of the technologist. In general these structures are managed inside the FAB and are focused on standard device properties. Hence their development and analysis is not driven by analog circuit blocks, which are sensitive or often used. Especially for DFM/Y of analog circuits the correlation between design and technology has to be defined. The knowledge of electrical behavior of test structures helps to improve the designer's sensitivity to technological questions. This paper presents a method to bring the PCM methodology into the analog circuit design to improve design performance, yield estimation and technology correlation. We show how both analog circuit and PCM blocks can be simulated and analyzed in the design phase.

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text

The Discrete Controller Synthesis (DCS) technique is used for automatic generation of correct-by-construction hardware controllers. For a given plant (a state-based model), and an associated control specification (a behavioral requirement), DCS generates a controller which, composed with the plant, guarantees the satisfaction of the specification. The DCS technique used relies on binary decision diagrams (BDDs). The controllers generated must be compliant with standard RTL hardware synthesis tools. Two main issues have been investigated: the combinational explosion, and the actual generation of the hardware controller. To address combinational explosion, common approaches follow the "divide and conquer" philosophy, producing modular control and/or decentralized control. Most of these approaches do not consider explicit communication between different components of a plant. Synchronization is mostly achieved by sharing of input events, and outputs are abstracted away. We propose an incremental DCS technique which also applies to communicating systems. An initial modular abstraction is followed by a sequence of progressive refinements and computations of approximate control solutions. The last step of this sequence computes an exact controller. This technique is shown to have an improved time/memory efficiency with respect to the traditional global DCS approach. The hardware controller generation addresses the control non-determinism problem in a specific way. A partially closed-loop control architecture is proposed, in order to preserve the applicability of hierarchical design. A systematic technique is proposed and illustrated, for transforming the automatically generated control equation into a vector of control functions. An application of the DCS technique to the correction of certain design errors in a real design is illustrated. To prove the efficiency of the incremental synthesis and controller implementation, a number of examples have been studied.

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