This thesis deals with the design of the 3,5" floppy drive emulator with ATMEGA microprocessor unit. The emulator has been designed according to the principles of designing electronic devices, there is also object-control application and firmware for a microcontroller, which supports MFM coding. The thesis also lists all the formats of data stored or transmitted along with some flowcharts.

This term paper deals with subject of wireless communication of city rail transport cars. In this paper are described individual modules for transmission and receiving of data containing communication between city rail transport cars and measures of siding switches. Then there are discussed possibilities of design of system for testing functionality of transmitting and receiving modules and the system is consequently designed. There are also described communication principles and protocol used for wireless communication and MODBUS protocol used for communication over RS-485 serial line. In the end was the system manufactured, completed and equipped with necessary software.

In recent years, there has been a strong need for the design of integrated  circuits showing low power consumption. It is possible to create intentionally approximate circuits which don't fully implement the specified logic behaviour, but exhibit improvements in term of area, delay and power consumption. These circuits can be used in many error resilient applications, especially in signal and image processing, computer graphics, computer vision and machine learning. This work describes an evolutionary approach to approximate design of arithmetic circuits and other more complex systems. This text presents a parallel calculation of a fitness function. The proposed method accelerated evaluation of 8-bit approximate multiplier 170 times in comparison with the common version. Evolved approximate circuits were used in different types of edge detectors.

Tato disertační práce se zabývá evolučním návrhem a optimalizací jak běžných, tak polymorfních digitálních obvodů. V práci jsou uvedena a vyhodnocena nová rozšíření kartézského genetického programování (Cartesian Genetic Programming, CGP), která umožňují zkrácení výpočetního času a získávání kompaktnějších obvodů. Další část práce se zaměřuje na nové metody syntézy polymorfních obvodů. Uvedené metody založené na polymorfních binárních rozhodovacích diagramech a polymorfním multiplexovaní rozšiřují běžné reprezentace digitálních obvodů, a to s ohledem na začlenění polymorfních hradel. Z důvodu snížení počtu hradel v obvodech syntetizovaných uvedenými metodami je provedena evoluční optimalizace založená na CGP. Implementované polymorfní obvody, které jsou optimalizovány s využitím CGP, reprezentují nejlepší známá řešení, jestliže je jako cílové kritérium brán počet hradel obvodu.

A simple methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environment, there is no modification of the comparator itself nor some unusual stimuli required. There is also no known restriction for the type of comparators to be analyzed.

Die vorliegende Arbeit behandelt den Entwurf eines ADCs nach dem sukzessiven Approximationsverfahren (SAR). Ausgehend von den Systemanforderungen erfolgt eine Ableitung der Spezifikation des zu entwerfenden ADCs. Theoretische Betrachtungen und Highlevelsimulationen in Matlab wählen die optimale Architektur der Einzelkomponenten - kapazitives DAC Array, Komparator, Ablaufsteuerung - aus. Die Implementation selbst findet für die Analogschaltungsteile auf Transistorebene und für die digitalen Komponenten auf RT-Ebene in VHDL statt. Sie bilden die Grundlage für die Realisierung des Layouts. In dem Zusammenhang stellt die Arbeit die gängigsten Matchingmethoden für elektronische Bauelemente vor. Abschließende PEX-Simulationen (parasitic Extraction) ermitteln die statischen (INL/DNL) wie dynamischen Kennwerte (SNR) des SAR-ADCs.:Abkürzungsverzeichnis iii Formelzeichen v 1 Einleitung 1 2 Grundlagen 2 2.1 Analog/Digital-Umsetzer 2 2.1.1 Umsetzungsverfahren 2 2.1.2 Statische Kennwerte 8 2.1.3 Dynamische Kennwerte 12 2.2 Technologie 17 2.2.1 Übersicht 17 2.2.2 MOS-Transistoren 17 2.2.3 Kapazitäten 18 2.2.4 Widerstände 18 2.3 Hardwarebeschreibungssprache 19 2.3.1 Übersicht 19 2.3.2 Zustandsautomat 19 2.3.3 Look-Ahead-Ausgang 20 3 Spezifikation 21 4 ADU-Topologie 23 4.1 Vorüberlegungen 23 4.1.1 Umsetzungsverfahren 23 4.1.2 Vergleich Widerstand/Kapazität 23 4.1.3 Differenziell Vs. Single-Ended 24 4.1.4 Kapazitätsarray 25 4.2 ADC High-Level Modell 30 4.2.1 Funktionsblöcke 30 4.2.2 Matlab/Simulink 31 4.2.3 Simulation 34 4.3 Parasitäre Effekte 37 4.3.1 Substratkapazität 37 4.3.2 Komparatoroffset 39 5 Schaltungsdesign & -simulation 41 5.1 Komparator 41 5.1.1 Spezifikation 41 5.1.2 Latch 41 5.1.3 Vorverstärker 43 5.1.4 Gesamtsystem 46 5.2 Schalter 46 5.2.1 Funktionsweise 46 5.2.2 Ladungseintrag 46 5.2.3 Dimensionierung & Simulation 47 5.3 Kapazitätsarray 51 5.4 SAR-Controller 51 5.4.1 Vorüberlegung 51 5.4.2 RTL Design 52 5.4.3 Simulation 55 5.4.4 Synthese 57 5.4.5 Optimierung 59 5.5 ADC (Toplevel) 59 5.5.1 Architektur 59 5.5.2 Simulation 61 6 Layout 64 6.1 Komparator 65 6.1.1 Vorverstärker 1 65 6.1.2 Vorverstärker 2 66 6.1.3 Dynamisches Latch 66 6.2 Transmission Gates 67 6.3 Kapazitätsarray 68 6.4 SAR-Controller 70 6.5 ADC (Toplevel) 70 6.6 PEX Simulation 72 6.6.1 Statischer Test 72 6.6.2 Dynamischer Test 73 7 Zusammenfassung 74 Literaturverzeichnis 76 Bücher 76 Skripte und Schriften 76 Internetlinks 78 Abbildungsverzeichnis 79 Tabellenverzeichnis 82 Anhang 84

Since the heyday of analogue synthesizers in the 70's, they have largely been replaced by digital hardware and software synthesizers. However, in recent years, there has been a revival in analogue designs, possibly due to its ``warmer" sound. This projects aims to take part of this renewal by building a simple analogue synth design with the most basic modules (e.g. oscillators, filters, mixers, amplifier), accompanied by a step sequencer for programming melodies. This will be done by designing circuits and implementing them on breadboards. The circuits were designed with inspiration from various online resources, along with theoretical analysis and simulation software for complex circuitry. The result is a fully functional synthesizer with four sawtooth oscillators. The only modules missing from the initial design are battery support and a line out output for recording the output of the synthesizer. The pitch specification was met as the oscillator did not differ from the expected frequency by more than $\pm$15 cents (hundredths of a semitone), for a range of five octaves. Some possible improvements include better step sequencer user friendliness by installing a display to indicate the notes, more robustness by implementing the synth on a circuit board instead of breadboard. Some improvements can be made for the synth. For example, a display for the step sequencer would facilitate melody programming. Moreover, implementing the synth on a circuit board instead of breadboards would greatly improve robustness and reduce the risk of sound disruptions.

<p>Glaucoma is the leading cause of irreversible blindness worldwide. While current therapies aim to lower elevated intraocular pressure (IOP) to prevent blindness, they often do not provide the desired long-term efficacy, can fail over time, and have systemic side effects. Electroceutical stimulation can be a solution to many of these current issues with glaucoma treatment, as it is believed to have fewer systemic side effects and quicker response times. The goal of this work is to develop and demonstrate a novel system using electrical stimulation to lower intraocular pressure. I present data from a human clinical study and an ongoing clinical trial of the IOPTx™ system, a wearable electroceutical for treating glaucoma, that provides preliminary evidence of efficacy and safety. <a>Furthermore, no current glaucoma treatments allow for closed-loop, continuous monitoring of IOP, requiring more frequent doctor visits or forcing patients and clinicians to operate in the dark. Using an electroceutical therapeutic device with closed-loop feedback and continuous IOP recording can improve glaucoma management. I combined a pressure sensor with this electroceutical therapy, implanted the sensor and stimulation coils in rabbits, and stimulated the eyes. However, to better understand the optimal stimulation parameters, long-term effects, and mechanisms of action, an integrated circuit is designed as part of a fully implantable, closed-loop device. The chip was fabricated in 0.18 </a>µm CMOS process and validated on the benchtop and <i>in vivo</i>. In the future, this electroceutical device has the potential to be a novel treatment for patients suffering from glaucoma.</p>

For multiplayer games, the performance of the server’s Central Processing Unit (CPU) is the main factor that limits the number of players on the server at the same time. Compared with the CPU, the Field-Programmable Gate Array (FPGA) architecture has no instructions set and no shared memory. Offloading some tasks from the CPU to the FPGA may help the CPU improve processing efficiency. This thesis explores which tasks on a CPU can be offloaded to a FPGA and how to design such a circuit system. The performance of the developed system also needs to be measured. We decided to offload communication tasks and data processing tasks to an FPGA. The result is that the FPGA server is available for work, the maximum number of users is 80, and the maximum network latency is 30-40 ms. The most important result is that a FPGA can be used as a multi-player server. One of the severe limitations of this design is the number of hardware resources. A 7-series FPGA is divided into several similar clock regions, which means the number of Flip Flop (FF)s near the same clock edge is fixed. If adding more FFs in the same component, the routing delay can not meet the set-up time requirements. Previously, people used the FPGA as the support accelerator to the server CPU. The CPU still works as a paramount communication link with one or several multi-connection parts and connects to the FPGA via the Peripheral Component Interconnect Express (PCIe) to use the FPGA to process data or pack/unpack Ethernet frames. We have designed and implemented a whole multi-connection server in a Hardware Description Language (HDL) and downloaded the resulting hardware in an FPGA. / I spel med flera spelare är serverns CPU-prestanda (Central Processing Unit) den viktigaste faktorn som begränsar antalet spelare som servern samtidigt kan hantera. Jämfört med CPU:n har en FPGA (Field-Programmable Gate Array) inga instruktioner och inget delat minne. Avlastning av vissa uppgifter från den CPU till FPGA:n kan hjälpa CPU:n att förbättra bearbetningseffektiviteten. I denna avhandling undersöks vilka uppgifter på en CPU som kan överföras till en FPGA och hur man utformar ett sådant kretsystem. Prestandan hos det utvecklade systemet måste också mätas. Vi har beslutat att avlasta kommunikationsuppgifter och databehandlingsuppgifter. till en FPGA. Resultatet är att FPGA-servern är tillgänglig för arbete, det maximala antalet användare är 80, och den maximala nätverksfördröjningen är 30-40 ms. Det viktigaste resultatet är att en FPGA kan användas som en server för flera spelare. En av de allvarliga begränsningarna med denna konstruktion är antalet hårdvaruresurser. En FPGA i 7-serien är uppdelad i flera liknande klockregioner, vilket innebär att antalet Flip Flop (FF)s nära en klocka är fast. Om man lägger till fler FF:er i samma komponent, kommer fördröjningen inte att uppfylla tidskraven för setup. Tidigare har folk använt sig av FPGA:n som en stödaccelerator till serverprocessorn. CPU:n fungerar fortfarande som en viktig kommunikationslänk med en eller flera anslutningar och ansluter till FPGA:n via Peripheral Component Interconnect Express (PCIe) för att använda FPGA:n till att bearbeta data och paketera/packa upp Ethernet-ramar. Vi har implementerat en hel server med flera anslutningar med hjälp av hårdvaruvarubeskrivande språk (HDL) och laddat ner den resulterande designen i en FPGA.

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