Thesis (M.S.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e Computação / Made available in DSpace on 2018-08-05T22:28:31Z (GMT). No. of bitstreams: 1 ManzanJunior_Donato_M.pdf: 1716370 bytes, checksum: 70e88e04a73f17039cb0ea8597b7b0cc (MD5) Previous issue date: 2005 / Resumo: Este trabalho descreve o desenvolvimento de um sensor de umidade relativa que tem como elemento sensor um polímero (poli(óxido de etileno-co-epicloridrina)84:16), cuja condutividade varia com a umidade. O polímero foi depositado por casting sobre um substrato cerâmico sobre o qual, por sua vez, foram depositados dois eletrodos em forma interdigitada aos quais é aplicada uma corrente alternada com forma de onda quadrada e amplitude DC nula. Este sinal de excitação é produzido por um circuito integrado que também realiza a leitura da tensão nos terminais do eletrodo. Além disto, o circuito contém um sensor de temperatura cuja informação é necessária para a correta leitura da umidade. Amostras do circuito integrado, cujo projeto é parte deste trabalho, foram fabricadas em tecnologia CMOS 0,35um e caracterizadas juntamente com o elemento sensor. Os resultados mais relevantes da caracterização do sensor desenvolvido são: Faixa de medição: máx 90%RH para evitar condensação; Sensibilidade do elemento sensor: 188,83W/%RH a 55%RH; Histerese: 3,4% a 55%RH; Temperatura de operação: 0 a 60oC; Tempo de resposta: +/-30s. A principal contribuição deste trabalho reside na proposição de um sensor de umidade que é composto de um elemento sensor polimérico e de um circuito integrado que realiza o condicionamento e leitura dos sinais envolvidos, constituindo deste modo uma solução robusta e de baixo custo / Abstract: This work describes the development of a relative-humidity sensor, which uses as sensing element a polymer (poly(ethylene oxide-co-epichlorohydrin)84:16) whose conductivity varies with humidity. The polymer was deposited by casting over a ceramic substrate, on which two interdigitized electrodes were previously deposited. An integrated circuit, also developed as part of the work, provides a square wave current with no DC component as excitation signal to the electrodes and reads the voltage across them. The developed integrated circuit also includes a temperature sensor, whose produced signal is used to yield the correct humidity measurement. Samples of the integrated circuit were fabricated in 0.35µm CMOS technology and were characterized together with the sensing element. The most relevant characteristics of the developed humidity sensor are: Measuring range: 90%RH max, to avoid condensing; Sensor element sensitivity: 188,83W/%RH at 55%RH; Hysteresis: 3,4% at 55%RH; Operating temperature: 0 to 60oC; Response time: +/-30s. The main contribution of this work is the proposition of a humidity sensor, which is based on a compound of a polymeric sensing element that operates in conjunction with an integrated circuit. The developed integrated circuit performs the necessary conditioning of the involved signals, in addition to include a temperature sensor. The developed humidity sensor has proven to be robust and can be produced at a relative low cost / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

No description available.

Optical sensors are among the sensors that are often used for distance measurements. An optical distance sensor is basically made of a light emitter (Tx) such as a light emitting diode (LED), a light receiver (Rx) such as a photosensitive transistor, and a circuit supporting the operation of the Tx and Rx. The distance measurement is made using the reflection technique in which the Tx emits a light to a target and the Rx receives the reflected light from the target. When designing such a sensor, the factors that affect the performance of measurements need to be taken into account. Among them are light intensity and wavelength. The purpose of this thesis project is to investigate and evaluate the optical sensors, in application towards distance measurement. To this purpose, three pairs of LEDs and phototransistors are selected which three distance sensors are made of. The lights from three LEDs have the wavelengths of 830, 880, and 940 nm, respectively, which are all in the infrared (IR) spectrum.  A circuit was made for each sensor in order to read the measurements and then calculate the distances, and then tested in a testbench. The testbench has a metal plate used as a measurement target which can be moved up and down by a motor. Each of the circuits was placed on the testbench’s base, and a microcontroller (Arduino Uno R3) was used to read the measurement of voltage (proportional to the light intensity) from the Rx as the distance to the target changes up to one meter. The measurement data is then presented on a graphical interface to analyse the relationship of light intensity with distance. Curve fitting and optimization techniques are applied to the data to construct a smooth function that approximately fits the data. An operating range where the distance can be reliably determined is determined for each unit. The circuit design and technique was proven to work for operating ranges up to one meter. A limited moving range of the testbench does not allow for experiments at distances higher than one meter and the microcontroller is ill fit for measuring low voltages, but these can be addressed by improving the measuring environment without changing the underlying technique. The test results of the distance measurement reveal that the three sensors give similar distance estimations between different configurations over an operating range of up to 0.9 meters. Future work should consider improving the circuit design to reduce power ripple and increasing operating range.

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, and reiterate on my design and see improvements and effects. The tool chain calculates power consumption, performance, temperature, and MTTF for a 'real life' circuit. Electric VLSI, an Electronic Design Automation tool, outputs a Spice file that yields parasitic quantities and spatial dimensions. LTspice, a high performance Spice simulator, was used to calculate the voltage and current data. Finally, I created MAP to monitor the voltage, current, and dimension data and process that in conjunction with HotSpot, a thermal modeling tool, to calculate a MTTF for each MOSFET. Analysis of the data from the software infrastructure showed that transistor sizing played a role in the MTTF. To maximize the MTTF of a transistor in a CMOS inverter, the activity of the pull-up transistor should be balanced with the transistor in the pull-down chain, ensuring the electric fields are balanced across both transistors. While it is impossible to completely balance an arbitrary CMOS circuit's activity for an arbitrary set of input signals, circuits can be intelligently skewed to help maximize the MTTF without increasing power consumption and without sacrificing circuit performance. Consequently, attaining a maximum MTTF does not come at a cost as it is possible to design a circuit with a high MTTF that performs better and uses less power than a circuit with low MTTF.

No description available.

In recent years, there has been an explosion of advancements in artificial intelligence, especially in language models. These models have become essential in aiding and providing information for various tasks. This study explores five proprietary and open-source large language models (LLMs) and examines their reliability and accuracy in selecting parts and constructing connections of ten circuit design tasks from our benchmark. During our investigations, we assessed that the default textual outputs from these LLMs could lead to ambiguous responses that are either too general or open to multiple interpretations. To enhance clarity, we developed an artificial intelligence (AI)-based pipeline that translates responses from LLMs into netlists, eliminating the need for further training or fine-tuning. Our study aims to highlight the reliability and accuracy of the default responses, develop a solution that provides a more explicit netlist description, and compare default and netlist outputs.