The co-optimization of energy and reserves has become a standard requirement in integrated markets. This is due to the inverse relationship that exists between energy and reserves. The provision of reserves generally reduces the amount of primary energy a generating unit can produce and vice versa. This suggests that these products should be procured through a simultaneous auction to ensure optimal procurement and pricing. Furthermore, forward markets dictate that this co-optimization of energy and reserves be done over a multi-period planning horizon. This dissertation addresses the problem of optimal scheduling and pricing of energy and reserves over a multi-period planning horizon using an optimal power flow formulation. The extension of the problem from a static optimization problem to a dynamic optimization problem is presented. Price definitions for energy and reserves in terms of shadow prices emanating from the optimization algorithm are provided. It is shown that the proposed formulation of prices leads to the cascading of reserve prices and eliminates the problem of “price reversal” where lower quality reserves are priced higher than higher ii quality reserves. Pricing conditions are also established for the downward substitution of higher quality reserves for lower quality reserves. The proposed pricing formulations are tested on the IEEE 24 Bus Reliability Test System and on the South African power network. The simulated results show that cascading of reserve prices does occur and that prices of different types of reserves are equal when downward substitution of reserves occurs. Zonal reserve requirements result in higher energy and reserve prices, which in term result in higher procurement costs to the system operator and higher profits to market participants. Congestion on the network also results in higher procurement costs to the system operator and higher profits to market participants in the case of zonal pricing of reserves. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Electrical, Electronic and Computer Engineering / unrestricted

It is extremely difficult to optimize a deep neural network (DNN) accelerator’s performance on various networks in terms of energy and/or latency because of the sheer size of the search space. Not only do DNN accelerators have a huge search space of different hardware architecture topologies and characteristics, which may perform better or worse on certain DNNs, but also DNN layers can be mapped to hardware in a huge array of different configurations. Further, an optimal mapping for one DNN architecture is not consistently the same on a different architecture. These two factors depend on one another. Thus there is a need for co-optimization to take place so hardware characteristics and mapping can be optimized simultaneously, to find not only an optimal mapping but also the best architecture for a DNN as well. This work presents Blink, a design space exploration (DSE) tool, which co-optimizes hardware attributes and mapping configurations. This tool enables users to find optimal hardware architectures through the use of a genetic algorithm and further finds optimal mappings for each hardware configuration using a pruned random selection method. Architecture, layers, and mappings are each sent to Timeloop, a DNN accelerator simulator, to obtain accelerator statistics, which are sent back to the genetic algorithm for next population selection. Through this method, novel DNN accelerator solutions can be identified without tackling the computationally massive task of simulating exhaustively.

A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO). / The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization.

[pt] O sistema elétrico de potência brasileiro, denominado Sistema Interli- gado Nacional – SIN, possui como órgão responsável pela operação o Op- erador Nacional do Sistema Elétrico – ONS. A fim de utilizar os recursos energéticos de forma a garantir a qualidade, confiabilidade e segurança no suprimento de energia elétrica ao menor custo total de operação, o oper- ador utiliza uma cadeia de modelos de otimização que subsidia a tomada de decisão no Programa Diário de Operação, implementado diariamente nas salas de controle do ONS e de agentes de geração para operação em tempo real. A etapa de Programação Diária do Operador Nacional do Sistema Elétrico busca estabelecer o despacho centralizado da geração e das reser- vas de potência a fim de atender à demanda prevista de energia elétrica considerando os limites da rede elétrica, das tecnologias de geração e a in- certeza de disponibilidade das unidades geradores e linhas de transmissão. Este trabalho propõe um modelo computacional programado em código aberto para a programação diária implementado na linguagem Julia. O modelo pertence à classe de modelos de unit commitment e considera a cootimização do despacho de geração e definição dos níveis de reservas em cada gerador do SIN para atender a critérios de segurança do tipo N − K . / [en] The Brazilian electric power system, called the National Interconnected System - SIN ( Sistema Interligado Nacional), has as its responsible institu- tion for operation the National Electric System Operator - ONS (Operador Nacional do Sistema Elétrico). In order to manage energy resources to en- sure quality, reliability and security of electricity supply at the lowest total operating cost, the operator uses a chain of optimization models that feeds the Daily Operation Program for decision-making, which is implemented everyday in the ONS and generators control rooms for real-time operation. The Daily Scheduling phase of the National Electric System Operator seeks to establish the centralized dispatch of generation and power reserves in order to meet the expected demand for electricity considering the limits of both the electrical grid and the generation technologies, along with the uncertainty of availability of generator units and transmission lines. This work proposes a computational model programmed in open-source for daily operation programming, implemented in the Julia language. The model be- longs to the unit commitment model class and it considers the generation dispatch cooptimization and reserve levels definition in each SIN generator to meet N-K safety criteria.

<div>Energy-efficient communication has remained the primary bottleneck in achieving fully energy-autonomous IoT nodes. Several scenarios including In-Sensor-Analytics (ISA), Collaborative Intelligence (CI) and Context-Aware-Switching (CAS) of the cluster-head during CI have been explored to trade-off the energies required for communication and computation in a wireless sensor network deployed in a mesh for multi-sensor measurement. A real-time co-optimization algorithm was developed for minimizing the energy consumption in the network for maximizing the overall battery lifetime of individual nodes.</div><div><br></div><div>The difficulty of achieving the design goals of lifetime, information accuracy, transmission distance, and cost, using traditional battery powered devices has driven significant research in energy-harvested wireless sensor nodes. This challenge is further amplified by the inherent power intensive nature of long-range communication when sensor networks are required to span vast areas such as agricultural fields and remote terrain. Solar power is a common energy source is wireless sensor nodes, however, it is not reliable due to fluctuations in power stemming from the changing seasons and weather conditions. This paper tackles these issues by presenting a perpetually-powered, energy-harvesting sensor node which utilizes a minimally sized solar cell and is capable of long range communication by dynamically co-optimizing energy consumption and information transfer, termed as Energy-Information Dynamic Co-Optimization (EICO). This energy-information intelligence is achieved by adaptive duty cycling of information transfer based on the total amount of energy available from the harvester and charge storage element to optimize the energy consumption of the sensor node, while employing event driven communication to minimize loss of information. We show results of continuous monitoring across 1Km without replacing the battery and maintaining an information accuracy of at least 95%.</div><div><br></div><div>Decades of continuous scaling in semiconductor technology has resulted in a drastic reduction in the cost and size of unit computing. This has enabled the design and development of small form factor wearable devices which communicate with each other to form a network around the body, commonly known as the Wireless Body Area Network (WBAN). These devices have found significant application for medical purposes such as reading surface bio-potential signals for monitoring, diagnosis, and therapy. One such device for the management of oropharyngeal swallowing disorders is described in this thesis. Radio wave transmission over air is the commonly used method of communication among these devices, but in recent years Human Body Communication has shown great promise to replace wireless communication for information exchange in a WBAN. However, there are very few studies in literature, that systematically study the channel loss of capacitive HBC for <i>wearable devices</i> over a wide frequency range with different terminations at the receiver, partly due to the need for <i>miniaturized wearable devices</i> for an accurate study. This thesis also measures and explores the channel loss of capacitive HBC from 100KHz to 1GHz for both high-impedance and 50Ohm terminations using wearable, battery powered devices; which is mandatory for accurate measurement of the HBC channel-loss, due to ground coupling effects. The measured results provide a consistent wearable, wide-frequency HBC channel loss data and could serve as a backbone for the emerging field of HBC by aiding in the selection of an appropriate operation frequency and termination.</div><div><br></div><div>Lastly, the power and security benefits of human body communication is demonstrated by extending it to animals (animal body communication). A sub-inch^3, custom-designed sensor node is built using off the shelf components which is capable of sensing and transmitting biopotential signals, through the body of the rat at significantly lower powers compared to traditional wireless transmissions. In-vivo experimental analysis proves that ABC successfully transmits acquired electrocardiogram (EKG) signals through the body with correlation accuracy >99% when compared to traditional wireless communication modalities, with a 50x reduction in power consumption.</div>