This thesis describes an investigation into the suitability of complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) devices for scientific imaging applications. CMOS APS offer a number of advantages over the established charge-coupled device (CCD) technology, primarily in the areas of low power consumption, high-speed parallel readout and random (X-Y) addressing, increased system integration and improved radiation hardness. The investigation used a range of newly designed Test Structures in conjunction with a range of custom developed test equipment to characterise device performance. Initial experimental work highlighted the significant non-linearity in the charge conversion gain (responsivity) and found the read noise to be limited by the kTC component due to resetting of the pixel capacitance. The major experimental study investigated the contribution to dark signal due to hot-carrier injection effects from the in-pixel transistors during read-out and highlighted the importance of the contribution at low signal levels. The quantum efficiency (QE) and cross-talk were also investigated and found to be limited by the pixel fill factor and shallow depletion depth of the photodiode. The work has highlighted the need to design devices to explore the effects of individual components rather than stand-alone imaging devices and indicated further developments are required for APS technology to compete with the CCD for high-end scientific imaging applications. The main areas requiring development are in achieving backside illuminated, deep depletion devices with low dark signal and low noise sampling techniques.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 143-145). Also available in electronic format on the Internet.

Orientador: Jacobus Willibrordus Swart / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-12T18:12:37Z (GMT). No. of bitstreams: 1 Campos_FernandodeSouza_D.pdf: 2206636 bytes, checksum: f20b690f268876e5aef018b4b97266ac (MD5) Previous issue date: 2008 / Resumo: O trabalho apresentado nesta tese endereça dois importantes desafios impostos pela evolução da tecnologia CMOS, a diminuição da responsividade das junções e a redução da tensão de alimentação. Um fotodetector de alta responsividade e um sistema de imagem CMOS multiamostrado no domínio do tempo são propostos nesta tese. Como fototransistor de elevada responsividade propõem-se nesta tese o uso do Transistor Bipolar Lateral Controlado por Porta (GC-LBJT) operando como fototransistor de 4 terminais. Apresenta-se a análise do princípio de funcionamento e o desenvolvimento de um circuito equivalente CC. A fotoresposta do GC-LBJT é investigada em duas diferentes configurações, coletor-comum com tensão porta-base constante e emissor-comum com tensão porta-emissor constante. A característica da fotoresposta é associada às equações do dispositivo em ambas as configurações mostrando os principais parâmetros do dispositivo que determinam o ganho. Na configuração coletor-comum, a característica da fotoresposta varia de aproximadamente linear a sublinear por meio da tensão de controle VGB. Na configuração emissor-comum, o dispositivo apresenta fotoresposta sublinear e baixa excursão para toda faixa de tensão de controle (VGB) utilizada. Explorando a característica controlável do GC-LBJT em ambas as configurações, o fototransistor GC-LBJT pode apresentar ganho e responsividade maiores do que 10+6 e 10+4 A/W respectivamente. Propõe-se o método de múltipla-amostragem para sistemas de imagem CMOS no domínio do tempo. O pixel é composto por um comparador e um circuito de memória de um bit. O método de múltipla-amostragem no domínio do tempo permite reduzir o circuito de memória integrado ao pixel de 8 bits tipicamente para um único bit. O resultado da amostra armazenado na memória de um bit no pixel é lida externamente de forma síncrona e o valor do sinal do pixel é codificado de acordo com o instante da amostra no tempo. O número de bits e a velocidade de operação do circuito limitam a dimensão máxima da matriz. Além disso, este trabalho apresenta a influência da não-linearidade da capacitância do fotodiodo na característica da fotoresposta dos sistemas de imagem CMOS no domínio do tempo. Estudo do comportamento do ruído de padrão fixo e o temporal em sistema de imagem no domínio do tempo também são apresentados / Abstract: This thesis adresses two important challenges imposed by CMOS technology trends, the reduction of the junctions's responsivity and voltages levels. A new photodetector with high responsivity and a multi-sampling time domain image system are investigated. This thesis proposes to use the gate controlled lateral bipolar junction transistor (GCLBJT) as a four terminal phototransistor as photodetector with high responsivity. This work presents the photopolarization principle, gain current mechanism of the GC-LBJT in conjuction with DC equivalent circuit development. The GC-LBJT photo response is analysed in two different configurations, common colector with constant gate-base voltage and common emmiter with constant gate-emitter voltage. The photoresponse is related to device equations in both configurations. In the common colector with constant gate-base voltage configuration the photo response characteristic changes from linear to sublinear according to the VGB control voltage. In the common emmiter configuration, the device presents sublinear photo response and small changes for full range of the VGB control voltage used. Exploring the GC-LBJT controllable characteristic, the GC-LBJT phototransistor presents high and controllable gain all over the range of irradiation used, for both configurations. The multi-sampling method for time domain CMOS image systems is proposed. The pixel's architecture is composed by a comparator and a single bit memory circuit. The multisampling method in time-domain allows reducing memory circuits integrated per pixel with eight bit tipically to a single bit. The sample result stored in the single bit memory of the pixel is externally read in a synchronous way and the pixel signal value is coded according to the sampling instant. The number of the bits and the speed of circuit's operation define the upper limit of the matrix size. In addition, this work presents the influence of non-linearity on photoresponse characteristic for systems operating in time domain. The behavior of fixed and temporal pattern noise study in time domain image system is also presented / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T17:33:52Z (GMT). No. of bitstreams: 1 Agostinho_PetersonRibeiro_M.pdf: 4830694 bytes, checksum: d3db6a2118db3df2774037e49df52865 (MD5) Previous issue date: 2006 / Resumo: Este trabalho descreve o procedimento de projeto de amplificadores operacionais rail-to-rail em tecnologia CMOS. Para isto, foram objetos desse processo quatro configurações distintas. As quatro topologias utilizam estágio de entrada rail-to-rail com controle de gm e estágio de saída classe-AB com controle de corrente quiescente. Como especificação para as três primeiras configurações estão tensão de alimentação de ± 0.9V, ganho de manha aberta em baixas freqüências de 60dB e freqüência de ganho unitário de 4MHz para uma carga externa de 10k? em paralelo com 10pF. A quarta configuração é uma nova topologia adaptada para que os transistores operem na região de inversão fraca, com o objetivo de reduzir o consumo de potência. Como especificação para esta configuração temos tensão de alimentação de ± 0.75V e minimização do consumo de potência. Os resultados obtidos a partir dos protótipos fabricados em tecnologia CMOS 0.35µm foram próximos às especificações. Uma placa de circuito impresso foi implementada para caracterização dos amplificadores e, além disso, foi utilizado nessa placa um amplificador comercial para realizar comparações / Abstract: This dissertation describes the process of designing rail-to-rail operational amplifiers in CMOS technology. To accomplish this, the author focused on four distinct structures. The four topologies have rail-to-rail input stage with gm-control circuit and Class-AB output stage with quiescent-current control. The specification of three configurations included the nominal power supply of ± 0.9V, minimum open-loop low-frequency gain of 60dB and unity-gain frequency of 4MHz driving an external load of 10k? in parallel with 10pF. The fourth one is a new topology adapted to operate with transistors in weak inversion, in order to decrease the power consumption. The specification included nominal power supply of ± 0.75V and minimization of power consumption. Prototypes of the amplifiers were fabricated in 0.35µm CMOS technology and the results were in good agreements with the specifications. A printed circuit board was implemented to test the amplifiers and, additionally, was inserted a commercial amplifier, to make comparisons / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientadores: Peter Jurgen Tatsch, Stanislav A. Moshkalev / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-21T09:15:24Z (GMT). No. of bitstreams: 1 Nunes_AlcineiMoura_D.pdf: 5060090 bytes, checksum: 2e93ff0bc8213b48460167d7e4cbbcc3 (MD5) Previous issue date: 2012 / Resumo: Neste trabalho foram desenvolvidas cinco aplicações de processos de corrosão por plasmas frios (temperatura ambiente), utilizando reatores dos tipos RIE (Corrosão por Íon Reativo) e ICP (Plasma Acoplado Indutivamente): Afinamento de porta de transistor CMOS - métodos convencionais como fotogravação, com resolução maior que 2 ?m, e corrosão por plasma em um reator RIE com as misturas gasosas SF6/CF4/CHF3 e SF6/CF4/N2, foram utilizados na obtenção de estruturas submicrométricas. A pressão foi variada de 50 mTorr a 150 mTorr e a potência de 30 W a 85 W. Corrosão de estruturas GaAs e AlGaAs para aplicação em transistores HEMT - as corrosões foram realizadas em um reator RIE com misturas de gás contendo SiCl4/Ar para a corrosão e O2/SF6/Ar para processo de limpeza da câmara; Corrosão de corpo para fabricação de sensores de pressão - foi utilizado um reator ICP e plasma de mistura gasosa SF6/Ar; Corrosão profunda para separação de patilhas utilizando métodos convencionais - foi utilizado um reator ICP para corrosão profunda dos canais. As misturas gasosas foram SF6/Ar, com polarização do eletrodo inferior para corrosão de Si (silício), e O2/Ar para remoção de fotorresiste; Teste de resistência de máscaras de Ni-P, Ni-B e SiO2 em processos de corrosão profunda e do tipo Bosch - as máscaras foram testadas em um reator ICP com plasma de misturas gasosas SF6/Ar e C4/F8. Em cada uma das aplicações foi feito um estudo sobre seus principais requerimentos, a fim de se obter o melhor compromisso entre os parâmetros do processo de corrosão / Abstract: This thesis is based on etching processes applications in cold plasmas (room temperature) using RIE (Reactive Ion Etching) and ICP (Inductively Coupled Plasma), as reactors, applied to specific areas of microelectronics and MEMS devices in semiconductors industries and laboratories. Five applications are presented: Thinning gate CMOS Transistor - conventional methods such as photolithography with resolution greater than 2 ?m and RIE reactor with gaseous mixtures: SF6/CF4/CHF3 and SF6/CF4/N2 were used to obtain structures below 1 ?m; GaAs and AlGaAs structures etching for HEMT transistors application - RIE reactor and mixtures containing SiCl4/Ar for etching and O2/SF6/Ar for cleaning were used; Bulk etching for pressure sensors - ICP reactor and gas mixture SF6/Ar were used; Deep Si etching for die separating - ICP reactor and gas mixtures SF6/Ar with bias for channel etching and O2/Ar for photoresist removal were used; Ni-P, Ni-B and SiO2 masks testing in deep etching processes - ICP reactor and gas mixtures as SF6/Ar and C4/F8 were used. In each applications a study of its main requirements was made, to achieve a better commitment between the parameters of the etching process / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.

L'industrie microélectronique est régie depuis plusieurs années par la loi de miniaturisation. En particulier, en technologie CMOS, les procédés de fabrication de l'oxyde permettant l'isolation électrique entre les transistors nécessitent sans cesse d'être améliorés pour répondre aux défis de cette loi. Ainsi, on est passé du procédé d'isolation par oxydation localisée de silicium (LOCOS) au procédé d'isolation par tranchées (STI). Cependant, ce dernier a montré pour les technologies en développement des limitations liées au remplissage non parfait par la silice de tranchées de moins en moins larges (Voiding) et au ''surpolissage'' des zones les plus larges (Dishing). Le procédé FIPOS (full isolation by porous oxidation of silicon) a été donc proposé comme solution alternative. Il est basé sur la formation sélective et localisée du silicium poreux qui est transformé ensuite en silice par un recuit oxydant. Cette piste prometteuse a constitué le point de départ de ce travail. Dans ce contexte, la thèse s'est focalisée sur deux axes principaux qui concernaient d'une part la maîtrise du procédé d'anodisation électrochimique pour la formation du silicium poreux et d'autre part l'optimisation du procédé d'oxydation. Dans une première partie de notre travail, l'analyse des caractéristiques courant-tension I-V menée sur le silicium durant son anodisation électrochimique a permis de montrer que la formation du silicium poreux dépend fortement de la concentration en dopants. Cette propriété nous a permis de développer une technique simple d'extraction du profil de dopage dans le silicium de type p par voie électrochimique. On a montré que la résolution en profondeur de cette technique est liée au niveau du dopage et s'approche de celle du SIMS (spectroscopie de masse d'ions secondaires) pour les fortes concentrations avec une valeur estimée à 60 nm/décade. Dans une deuxième partie, nous avons mis en évidence la formation localisée du silicium poreux oxydé. En effet, un choix judicieux du potentiel d'anodisation permet de rendre poreux sélectivement des régions fortement dopées implantées sur un substrat de silicium faiblement dopé. Ces régions sont ensuite transformées en oxyde par un recuit oxydant. Par ailleurs, les conditions optimales des processus d'oxydation et d'anodisation permettant d'obtenir un oxyde final de bonne qualité diélectrique sont analysées.