En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus de 50 000 personnes meurent subitement en raison d'arythmies cardiaques. L'identification des patients à risque élevé de décès soudain est toujours un défi. Pour détecter les arythmies cardiaques, actuellement Holter est généralement utilisé pour enregistrer les signaux électrocardiogramme (ECG) à 1~3 dérivations pendant 24h à 72h. Cependant l'utilisation de Holter est limitée parmi la population en raison de son encombrement (pas convivial) et de son coût. Un Holter mono puce portable nommé SoC-Holter qui permet d'enregistrer 1 à 4 dérivations est introduit. Le déploiement d'un réseau de capteurs sans fil exige que chaque SoC-Holter soit peu encombrant et peu cher, et consomme peu d'énergie. Afin de minimiser la consommation d'énergie et le coût du système, la technologie Complementary Metal Oxide Semiconductor (CMOS) (0.35μm) est utilisée pour la première implémentation de SoC-Holter. Puis une nouvelle méthode de détection basée sur Acquisition Comprimée (CS) est introduite pour résoudre les problèmes de consommation d'énergie et de capacité de stockage de SoC-Holter. Le principe premier de cette plate-forme est d'échantillonner les signaux ECG sous la fréquence de Nyquist 'sub-Nyquist' et par la suite de classer directement les mesures compressées en états normal et anormal. Minimiser le nombre de fils qui relient les électrodes à la plate-forme peut rendre l'utilisateur de SoC-Holter plus confortable, car deux électrodes sont très proches sur la surface du corps. La différence ECG enregistrée est analysée à l'aide de Vectocardiogramme (VCG). Les résultats expérimentaux montrent qu'une approche intégrée, à faible coût et de faible encombrement (SoC-Holter) est faisable. Le SoC-Holter consomme moins de 10mW en fonctionnement. L'estimation des paramètres du signal acquis est effectuée directement à partir de mesures compressées, éliminant ainsi l'étape de la reconstruction et réduisant la complexité et le volume des calculs. En outre, le système fournit les signaux ECG compressés sans perte d'information, de ce fait il réduit significativement la consommation d'énergie pour l'envoi de message et l'espace de stockage mémoire. L'effet de placement des électrodes est évalué sur la QRS complexe lorsqu'il a enregistré avec deux électrodes adjacentes. La méthode est basée sur l'algorithme de 'QRS-VCG loop alignment'. La méthode moindre carré est utilisée pour estimer la corrélation entre une boucle VCG observée et une boucle de référence en respectant les transformations de rotation et la synchronisation du temps. Les emplacements d'électrodes les moins sensibles aux interférences sont étudiés.

The objective of this research is to develop novel capacitive micromachined ultrasonic transducer (CMUT) arrays for intravascular ultrasonic (IVUS) imaging along with the fabrication processes to allow for monolithic integration of CMUTs with custom CMOS electronics for improved performance. The IVUS imaging arrays include dual-ring arrays for forward-looking volumetric imaging in coronary arteries and annular-ring arrays with dynamic focusing capabilities for side-looking cross sectional imaging applications. Both are capable of integration into an IVUS catheter 1-2 mm in diameter. The research aim of monolithic integration of CMUTs with custom CMOS electronics has been realized mainly through the use of sloped sidewall vias less than 5 µm in diameter, with only one additional masking layer as compared to regular CMUT fabrication. Fabrication of CMUTs has been accomplished with a copper sacrificial layer reducing isolation layers by 50%. Modeling techniques for computational efficient analysis of CMUT arrays were developed for arbitrary geometries and further expanded for use with larger signal analysis. Dual-ring CMUT arrays for forward-looking volumetric imaging have been fabricated with diameters of less than 2 mm with center frequencies at 10 MHz and 20 MHz, respectively, for an imaging range from 1 mm to 1 cm. These arrays, successfully integrated with custom CMOS electronics, have generated 3D volumetric images with only 13 cables necessary. Performance from optimized fabrication has reduced the bias required for a dual-ring array element from 80 V to 42 V and in conjunction with a full electrode transmit array, it was shown that the SNR can be improved by 14 dB. Simulations were shown to be in agreement with experimental characterization indicated transmit surface pressure in excess of 8 MPa. For side-looking IVUS, three versions of annular CMUT arrays with dynamic focusing capabilities have been fabricated for imaging 1 mm to 6 mm in tissue. These arrays are 840 µm in diameter membranes linked to form 8 ring elements with areas that deviate by less than 25 %. Through modeling and simulation undesirable acoustic cross between ring elements was reduced from -13 dB to -22 dB.

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

Orientador: José Alexandre Diniz / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-21T10:50:41Z (GMT). No. of bitstreams: 1 Silva_AudreyRoberto_M.pdf: 3023922 bytes, checksum: ee750f675d01f2b3ceebd5d74149b16e (MD5) Previous issue date: 2012 / Resumo: Este trabalho apresenta o desenvolvimento de células fotovoltaicas de junção n+/p em substratos de Si com processos de fabricação totalmente compatíveis com a tecnologia CMOS (Complementary Metal Oxide Semiconductor). Os processos compatíveis desenvolvidos neste trabalho sao as técnicas: i) de texturização da superfície do Si, com reflexao da superficie texturizada de 15% obtida com a formação de micro-pirâmides (alturas entre 3 e 7 ?m), utilizando-se solução alcalina de NH4OH (hidróxido de amônia), que e livre da contaminação indesejável por íons de Na+ e K+ quando se utiliza soluções tradicionais de NaOH e de KOH, respectivamente, e ii) de deposição ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) da camada antirrefletora (ARC) de SiNX (nitreto de silício), que e executada em temperatura ambiente, portanto pode ser feita apos a finalização da célula sem danificar trilhas metálicas e alterar a profundidade da junção n+/p. A caracterização desta camada ARC mostrou que o nitreto tem índice de refração de 1,92 e refletância mínima de 1,03%, o que e um excelente resultado para uso em células solares (ou fotovoltaicas). Foram fabricadas cinco series de células fotovoltaicas, utilizando-se a texturização com NH4OH e a camada antirrefletora de nitreto de Si. Em quatro series utilizou-se o processo de implantação de íons de fósforo (31P+), com posterior recozimento, para a formação da região n+, enquanto que na quinta serie foi utilizado o processo de difusão térmica. As eficiências máximas para as células fabricadas são de 9% e de 12%, respectivamente, para as células feitas utilizando os processos de implantação e de difusão térmica, indicando que a implantação de íons causa danos na rede cristalina do silício, que o posterior recozimento não consegue corrigir, o que reduz a eficiência da célula / Abstract: This work presents the development of photovoltaic cells based on n+/p junction in Si substrates, with fully compatible fabrication processes with CMOS technology. The compatible processes, which are developed in this study, are the techniques: i) of Si surface texturing, with the textured surface reflection of 15% obtained by the formation of micro-pyramids (heights between 3 and 7 ?m) using NH4OH (ammonium hydroxide) alkaline solution, which is free of undesirable contamination by Na + and K + ions, when NaOH and KOH traditional solutions are used, respectively, and ii) of the ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) deposition of SiNx (silicon nitride) anti-reflective coating (ARC), which is carried out at room temperature and can be performed after the end of cell fabrication without damage on metallic tracks and without variation of n+/p junction depth. The ARC coating characterization presented that the silicon nitride has a refractive index of 1.92 and a minimum reflectance of 1.03%, which is an excellent result for application in solar (or photovoltaic) cells. Five series of photovoltaic cells were fabricated, using the NH4OH solution texturing and the silicon nitride antireflective coating. In the first four series, phosphorus (31P+) ion implantation process, with subsequent annealing to get the region n+, was used, while, in the fifth series was used the thermal diffusion process. The maximum efficiency values are of 9% and 12%, respectively, for cells, which were fabricated using the ion implantation and thermal diffusion processes, indicating that the ion implantation damages the silicon crystal lattice and the subsequent annealing cannot rectify, which reduces the cell efficiency / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors to sub-100nm requires replacement of conventional Silicon dioxide layer with high dielectric constant (K) material for gate dielectric. Among the various high-K dielectrics that have been studied, HfO2 is found to be a promising candidate because of its high dielectric constant (~25), large band gap (5.68 eV), thermodynamic stability and good interface with Si. The HfO2 films have already been deposited using different growth techniques such as Atomic layer Deposition (ALD), Metalorgonic Chemical Vapor Deposition (MOCVD) and Pulsed Laser Deposition (PLD). Ion Assisted Deposition (IAD) is a novel technique that has been successfully employed to produce optical coatings of required quality. This growth technique presents many advantages over the other techniques such as formation from solid oxide sources, low growth temperatures (25-3000C) and film densification by ion bombardment. Hence this technique has been used to prepare HfO2 films in the present investigations. This thesis presents the structural, optical and electrical properties of HfO2 thin films prepared by Ion assisted deposition (IAD). The suitability of Ion assisted deposition process and the importance of investigations on the influence of process parameters on the film characteristics have been brought out in the process parameters-structure-composition and properties correlation presented in this thesis. The aim of this work is to process and characterize HfO2 films and investigate the influence of process parameters on the structure, composition and properties of the films to identify their suitability for CMOS gate applications. HfO2 films were deposited on p-type Si (100) wafers by Ion assisted deposition in an electron beam evaporation (Leybold,L-560) system. Pre-bombardment of the substrates with Argon ions has been done to remove any native oxide layer formation on Silicon by using a hallow cathode ion source (DENTON VACUUM CC103). During the film deposition a collimated oxygen ion beam, generated from the ion source is directed towards the substrate. The oxygen ion current is controlled by adjusting the voltage applied to the ion source and the oxygen flow through the ion source. The oxygen ions bombard the film as it grows and in that process improves its packing density as well as its stoichiometry. Keeping the deposition rate and thickness constant, HfO2 films have been deposited by varying Ion Current, Ion energy and substrate temperature. MOS capacitors were fabricated with Aluminum as gate electrode deposited by thermal evaporation. Ellipsometry techniques have been used to measure the optical thickness of the films. The interfacial layer (IL) formed at the HfO2/ Si interface was investigated by using Fourier transform Infrared spectroscopy (FT-IR). The structural characterization was carried out by X-ray diffraction technique. The high frequency capacitance-voltage and DC leakage current characteristics were measured to analyze the electrical characteristics of MOS capacitors. The effect of post deposition annealing (PDA) of the films at 600°C and 700ºC in Forming Gas (15%H2+85%N2) ambient and Post metallization annealing (PMA) at 400ºC in the same ambient was also investigated to observe the changes in electrical characteristics. The initial step of this work was to compare the characteristics of the films deposited by reactive evaporation and Ion assisted deposition which confirmed the superiority of the quality of IAD coatings and justified the need to proceed further with a more detailed study on the influence of various parameters on the properties of IAD coatings. HfO2 films deposited on substrates maintained at 1000C exhibited better structural, Optical and Electrical properties. The leakage current in these films were lower which has been attributed to silicate free interface as confirmed by XRD studies. Investigations on films deposited with oxygen ion beams of different currents in the range 20 to 40mA indicated that the films deposited at 20mA ion current showed better electrical properties. Better stoichiometry of these films as indicated by FT IR studies was one of the reasons for their improved performance. Annealing of these films at 6000C and 7000C in FGA medium resulted in creation of silicates and silicides at the interface thereby increasing the leakage currents and degraded the film properties. The films deposited with oxygen ion beams generated with a driving voltage 265V showed better structural and optical properties with silicate free interface compared with low and high driving voltages. Among all the films, the maximum dielectric constant of about 21.9 with a minimum EOT of 5.5 nm corresponding to a film deposited at ion current 20mA with PMA 400°C in FG ambient for 20minites is achieved. The lowest value of interface charge density achieved is 2.7 x1012 per cm-2 eV-1 corresponding to the sample deposited at substrate temperature 100°C with deposition rate of 0.5Å/sec followed by post metallization annealing at 400°C in forming gas for 20minutes. The range of Dit values that were obtained are varying from 2.7x 1012 – 16.7x1012 cm-2eV-1.It was also found that, the samples deposited at higher ion currents show lower Dit values than the samples deposited at lower ion currents. From the I−V analysis, the leakage current density is found to be comparatively less in IAD than in reactive evaporation. Leakage current increases with increase in substrate temperature and the same trend is observed with annealed films also. The lowest leakage current density of 1.05x10–8 A/cm2 at a gate bias of 1V was observed in the films deposited at substrate temperature 1000C. The present thesis focused on the suitability of the Ion Assisted deposition process for the preparation of HfO2 films for high-K gate dielectric application and the importance of investigations on the influence of process parameters on the film characteristics.

Orientador: José Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-26T13:53:46Z (GMT). No. of bitstreams: 1 Tercariol_WalterLuis_D.pdf: 1322557 bytes, checksum: 4f45518a1a62907cd9a61afa627408c3 (MD5) Previous issue date: 2014 / Resumo: Este trabalho visa compilar três contribuições na melhoria dos projetos de reguladores de tensão com unidades de bombeamento de carga embutidos (células elevadoras de tensão Dickson - BC). A primeira aborda uma técnica inovadora de arranque na partida deste módulo elevador quando habilitado. Este projeto se refere à aceleração da inicialização do modulo BC, tendo como objetivo a diminuição do intervalo de tempo da rampa ascendente da tensão de saída Vo até atingir o nível alvo de regulação. A técnica consiste em gerenciar o aumento da freqüência do relógio de bombeamento entregue as unidades de bombeamento durante a fase de subida, quando a regulação estiver estabelecida o sistema se regenera voltando ao estado original de freqüência de bombeamento natural. Uma segunda proposta inovadora de projeto é referente à homogeneização e redução da aleatoriedade da ondulação da tensão de saída Vo, referente ao regulador com o modulo BC embutido, baseado em comparadores com trava, com proposta de redução do erro de comparação devido ao efeito aleatório durante o estagio de comparação comumente encontrado neste tipo de abordagem, a técnica consiste em suprimir o acoplamento capacitivo nocivo durante a fase de isolamento elétrico no processo de comparação mantendo o espelho de corrente do comparador na região de saturação. Esta técnica visa proporcionar uma redução significativa da capacitância de desacoplamento utilizada para filtragem da tensão Vo. Uma terceira e última contribuição é referente a uma inovadora técnica de medição indireta da tensão de saída Vo do regulador com módulo BC baseada em uma medida simples e precisa dos pares tensão da porta e fonte (VPS) e corrente elétrica do dreno (Idreno) de um dispositivo NMOS de alta tensão adicionado de modo que duas tensões conhecidas (preestabelecidas) são aplicadas na porta do dispositivo e as respectivas correntes de dreno são mensuradas e uma terceira desconhecida (oriunda do regulador elevador BC) desconhecida pode ser extrapolada de forma simples. Esta técnica visa ser útil para medição de reguladores de baixa potencia pois o carregamento do regulador (Vo) é quase nulo.Todas as inovações e melhorias propostas foram analisadas em veículos de teste (silício) e com as provas de conceito, feitas em simulações elétricas / Abstract: This work aims to compile contributions in improving designs based on voltage regulators with voltage elevator with built-in charge pump CP. The first deals with an innovative technique rump-up this module when enabled. This project refers to the acceleration of startup the CP module, aiming at the reduction of the period of stabilization of the ramp output voltage Vo to the level of regulation target. The technique is to manage increasing the frequency of pumping clock during the phase of rump up and when the setting established the system regenerates back to the original state pumping frequency. A second innovative project proposal was made on the homogenization and reduction of the ripple of the output voltage Vo, referring to the regulator with the |CP module, based on latch comparators , alignment error reduction proposal because of the random effect during the stage comparison commonly found in this type of approach, the technique is to remove the harmful capacitive coupling during electrical isolation phase on the comparison keeping the comparator current mirror in saturation region. This technique aims to provide a significant reduction in the decoupling capacitance used for filtering the voltage Vo. A third and final contribution is related to an innovative technique of indirect measurement of the output voltage Vo of the regulator module CP, based on a simple and accurate measure of the gate voltage and couples the drain electric current of a high voltage NMOS device / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Orientador: Jose Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T10:56:11Z (GMT). No. of bitstreams: 1 Amaral_WellingtonAvelinodo.pdf: 14948298 bytes, checksum: 62522f5a0f70fd9563d5ac2c4c4652e2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho teve como finalidade o projeto e prototipagem de uma referência de tensão CMOS (Complementary Metal Oxide Semiconductor) baseada na tensão de limiar do transistor MOS (Metal Oxide Semiconductor). A inovação apresentada neste trabalho é a utilização de uma arquitetura original e com alto desempenho. Nas medidas realizadas em laboratório o circuito apresentou uma variação de 11ppm/0C. Desempenho este comparável às referências do tipo bandgap. Também foi projetado um sensor de temperatura com coeficiente térmico igual a 1mV/0C. Portanto, dois circuitos foram enviados para fabricação (o circuito ceinv35 e o circuito ceinv66). O circuito ceinv35, utilizando suas estruturas de trimmer, pode operar como referência de tensão ou como sensor de temperatura. O circuito ceinv66 foi a principal configuração estudada. Ele utiliza um circuito extrator de Vth, um circuito de start-up e um amplificador operacional. O circuito extrator de Vth utiliza uma topologia inovadora. Nos dois circuitos (ceinv35 e ceinv66) foram utilizadas estruturas de trimmer para possibilitar ajustes externos. No capítulo de introdução é apresentado um "overview" dos circuitos utilizados como referência de tensão. São analisadas algumas referências do tipo bandgap e algumas técnicas usualmente utilizada para o projeto de referências de tensão CMOS. No capítulo 2 são analisados o princípio de funcionamento e todo o equacionamento do circuito proposto. No capítulo 3 são apresentados os resultados de simulação. O circuito ceinv35 apresentou um coeficiente térmico igual a 1mV/0C, funcionando ele como sensor de temperatura. Já operando como referência de tensão, a variação apresentada foi de 4:06ppm/0C. O circuito ceinv66 apresentou uma variação de apenas 3:14ppm/0C. O capítulo 4 cobre o projeto dos layouts dos circuitos. Eles foram projetados utilizando a tecnologia da AMS (Austria Microsystems) de comprimento mínimo de canal igual a 0:35_m. No capítulo 5 são apresentados os resultados da extração de parasitas dos circuitos. Após esta análise foi verificada a necessidade de reajuste dos circuitos, utilizando as estruturas de trimmer. No capítulo 6 são fornecidos os resultados experimentais dos dois circuitos. No capítulo 7 é apresentada uma alternativa para o projeto da referência de tensão sem a necessidade da utilização do circuito de start-up. Neste mesmo capítulo também é apresentada uma proposta de metodologia para projeto dos trimmers do circuito. No capítulo 8 são discutidas as inovações propostas neste trabalho e algumas conclusões sobre o projeto apresentado. / Abstract: The objective of this work is to design and prototype a CMOS voltage reference based on the threshold voltage of the MOS transistor. The innovation presented in this work is the use of an original architecture with high performance. In the laboratory measurements the circuit presented 11ppm/0C of variation. This performance is comparable to the bandgap references. A temperature sensor was also designed and presented a temperature coefficient of 1mV/0C. Therefore, two circuits were prototyped (the ceinv35 circuit and the ceinv66 circuit). The circuit ceinv35, using the trimmer structures, can operate as a voltage reference or a temperature sensor. The circuit ceinv66 was the main topology studied. It uses a Vth extractor circuit, a start-up circuit and an operational amplifier. The Vth extractor circuit uses an original topology. In both circuits (ceinv35 and ceinv66) were used trimmer structures to make possible off-chip adjusts. In the introduction chapter is presented an overview of the circuits used as voltage references. Some bandgap references and some techniques used to design CMOS voltage references are analyzed. In chapter 2 are shown the operation principles and the equations extracted of the proposed circuit. In chapter 3 are shown the simulation results. The circuit ceinv35 presented a temperature coefficient of 1mV/0C, working as a temperature sensor. On the other side, working as a voltage reference, the variation presented was 4:06ppm/0C. The circuit ceinv66 presented a variation of just 3:14ppm/0C. The chapter 4 covers the layout design of the circuits. The AMS (Austria Microsystems) technology with a minimum channel length of 0:35_m was used. In chapter 5 are presented the parasitic extraction simulations. After this analyses new adjusts were made in the circuits. The trimmers structures were used for this adjusts. In chapter 6 are provided the experimental results of both circuits. In chapter 7 is presented an alternative for the voltage reference design without using a start-up circuit. In this chapter is also presented a methodology for the trimmers design. In chapter 8 are discussed the proposed innovations and some conclusions about the design presented. / Universidade Estadual de Campi / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

L’industrie microélectronique est régie depuis plusieurs années par la loi de miniaturisation. En particulier, en technologie CMOS, les procédés de fabrication de l’oxyde permettant l’isolation électrique entre les transistors nécessitent sans cesse d’être améliorés pour répondre aux défis de cette loi. Ainsi, on est passé du procédé d’isolation par oxydation localisée de silicium (LOCOS) au procédé d’isolation par tranchées (STI). Cependant, ce dernier a montré pour les technologies en développement des limitations liées au remplissage non parfait par la silice de tranchées de moins en moins larges (Voiding) et au ‘‘surpolissage’’ des zones les plus larges (Dishing). Le procédé FIPOS (full isolation by porous oxidation of silicon) a été donc proposé comme solution alternative. Il est basé sur la formation sélective et localisée du silicium poreux qui est transformé ensuite en silice par un recuit oxydant. Cette piste prometteuse a constitué le point de départ de ce travail. Dans ce contexte, la thèse s’est focalisée sur deux axes principaux qui concernaient d’une part la maîtrise du procédé d’anodisation électrochimique pour la formation du silicium poreux et d’autre part l’optimisation du procédé d’oxydation. Dans une première partie de notre travail, l’analyse des caractéristiques courant-tension I-V menée sur le silicium durant son anodisation électrochimique a permis de montrer que la formation du silicium poreux dépend fortement de la concentration en dopants. Cette propriété nous a permis de développer une technique simple d’extraction du profil de dopage dans le silicium de type p par voie électrochimique. On a montré que la résolution en profondeur de cette technique est liée au niveau du dopage et s’approche de celle du SIMS (spectroscopie de masse d'ions secondaires) pour les fortes concentrations avec une valeur estimée à 60 nm/décade. Dans une deuxième partie, nous avons mis en évidence la formation localisée du silicium poreux oxydé. En effet, un choix judicieux du potentiel d’anodisation permet de rendre poreux sélectivement des régions fortement dopées implantées sur un substrat de silicium faiblement dopé. Ces régions sont ensuite transformées en oxyde par un recuit oxydant. Par ailleurs, les conditions optimales des processus d’oxydation et d’anodisation permettant d’obtenir un oxyde final de bonne qualité diélectrique sont analysées. / The microelectronic industry is still ruled up to now by the law of miniaturization or scaling. In particular, in CMOS (complementary metal-oxide semiconductor) technology, the oxide allowing electric isolation between p- and n-MOS transistors has also been scaled down and has then exhibited different technological processes going from LOCOS (local oxidation of silicon) to STI (shallow trench isolation) and arriving to FIPOS (full isolation by porous oxidation of silicon). The latter seems to be the most promising alternative solution that can overcome actual limitations of voiding and dishing encountered in the STI process. The approach, which is based on selective formation of porous silicon and its easy transformation to silicon dioxide, has aroused our motivation to be well studied. In this context, the PhD project has first focused on the understanding of electrochemical porous silicon formation, and then on the study of porous silicon oxidation. In a first part of our work, we emphasize the dependence of porous silicon formation with the silicon doping concentration through the investigation of current-voltage I-V characteristics measured on p- and n-type silicon electrodes during electrochemical anodization. Taking advantage of this dependence, we have developed a very simple electrochemical method allowing an accurate determination of doping profiles in p-type silicon. It has been shown that the depth resolution of the technique is readily linked to the doping level and it approaches that of the secondary ion mass spectroscopy (SIMS) analysis for high doping concentrations with an estimated value of 60 nm/decade. In a second step, we highlight the selective formation of oxidized porous silicon. In fact, with a correct choice of the applied potential during anodization, only highly doped regions implanted on a lightly doped silicon wafer are preferentially turned into porous silicon and subsequently oxidized. Furthermore, we give the optimum conditions for oxidation and anodization processes which result in an insulating oxide of reliable dielectric properties.

La croissance continue et rapide du trafic de données dans les infrastructures de télécommunications, impose des niveaux de débit de transmission ainsi que de puissance de traitement de l’information, que les capacités intrinsèques des systèmes et microcircuits électroniques ne seront plus en mesure d’assurer à brève échéance : le développement de nouveaux scenarii technologiques s’avère indispensable pour répondre à la demande de bande passante imposée notamment par la révolution de l’internet, tout en préservant une consommation énergétique raisonnable. Dans ce contexte, l’intégration hétérogène fonctionnelle sur silicium de dispositifs photoniques à émission par la surface de type VCSEL utilisant des miroirs large-bandes ultra-compacts à cristaux photoniques constitue une stratégie prometteuse pour surmonter l’impasse technologique actuelle, tout en ouvrant la voie à un développement rapide d’architectures et de systèmes de communications innovants dans le cadre du mariage entre photonique et micro-nano-électronique. / The ever-growing demand for high-volume fast data transmission and processing is nowadays rapidly attaining the intrinsic limit of microelectronic circuits to offer high modulation bandwidth at reasonable power dissipation. Silicon photonics is set to break the technological deadlock aiming at a functional photonics-on-CMOS integration for innovative optoelectronic systems paving the way towards next-era communication architectures. Among the others photonic building blocks such as photodiodes, optical modulators and couplers, power-efficient compact semiconductors sources in the near-infrared telecommunication bands, characterized by performing modal features as well as thermal resiliency constitute an essential landmark to be achieved. Within such context, InP-based long-wavelength vertical-cavity surface-emitting lasers (VCSELs) using one-dimensional Si/SiO2 photonic crystals as wideband compact mirrors are proposed as next generation emitters for CMOS integration.