This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

No description available.

This dissertation presents analog circuit analysis and design from a nonlinear dynamics perspective. An introduction to fundamental concepts of nonlinear dynamical systems theory is given. The procedure of nondimensionalization is used in order to derive the state space representation of circuits. Geometric tools are used to analyze nonlinear phenomena in circuits, and also to develop intuition about how to evoke certain desired behavior in the circuits. To predict and quantify non-ideal behavior, bifurcation analysis, stability analysis and perturbation methods are applied to the circuits. Experimental results from a reconfigurable analog integrated circuit chip are presented to illustrate the nonlinear dynamical systems theory concepts. Tools from nonlinear dynamical systems theory are used to develop a systematic method for designing a particular class of integrated circuit sinusoidal oscillators. This class of sinusoidal oscillators is power- and area-efficient, as it uses the inherent nonlinearity of circuit components to limit the oscillators' output signal amplitude. The novel design method that is presented is based on nonlinear systems analysis, which results in high-spectral purity oscillators. This design methodology is useful for applications that require integrated sinusoidal oscillators that have oscillation frequencies in the mid- to high- MHz range. A second circuit design example is presented, namely a bandpass filter for front end auditory processing. The bandpass filter mimics the nonlinear gain compression that the healthy cochlea performs on input sounds. The cochlea's gain compression is analyzed from a nonlinear dynamics perspective and the theoretical characteristics of the dynamical system that would yield such behavior are identified. The appropriate circuit for achieving the desired nonlinear characteristics are designed, and it is incorporated into a bandpass filter. The resulting nonlinear bandpass filter performs the gain compression as desired, while minimizing the amount of harmonic distortion. It is a practical component of an advanced auditory processor.

The author begins with a short introduction to current neural network practices and pitfalls including an in depth discussion of the meaning behind the equations. Specifically, a description of the underlying processes involved is given which likens training to the biological process of cell differentiation. Building on these ideas, an improved method of generating integer based binary neural networks is developed. This type of network is particularly useful for the optical character recognition problem, but methods for usage in the more general case are discussed. The new method does not use training as such. Rather, the training data is analyzed to determine the statistically significant relationships therein. These relationships are used to generate a neural network structure that is an idealization of the trained version in that it can accurately extrapolate from existing knowledge by exploiting known relationships in the training data. The paper then turns to the design and testing of a VLSI CMOS chip which was created to utilize the new technique. The chip is based on the MOSIS 2Jlm process using a 2200A x 2200A die that was shaped into a special purpose microprocessor that could be used in any of a number of pattern recognition applications with low power requirements and/or limiting considerations. Simulation results of the methods are then given in which it is shown that error rates of less than 5% for inputs containing up to 30% noise can easily be achieved. Finally, the thesis concludes with ideas on how the various methods described might be improved further. / Master of Science

This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit synthesis. The conversion of data path synthesis is done in this thesis. In the DIADES system a digital system is described on the behavioral level in terms of variables and operations using the language ADL. The digital system described in ADL is compiled to a format called GRAPH language. In the GRAPH language the behavior of a digital system is represented by a specific sequence of program statements. The descriptions in the GRAPH language is compiled to a format called STRU CT language. The system is described in the STRU CT language in terms of lists of nodes and arrows. The main task of this thesis is to convert the descriptions in the GRAPH language and the descriptions in the STRUCT language to the VHDL format. All the generated VHDL Code will be Mentor Graphics VHDL format compatible, and all the VHDL code can be compiled, simulated and synthesised by the Mentor Graphics tools.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

The notion of designing circuits based on charge sensing, charge adaptation, and charge programming is explored in this research. This design concept leads to a low-power capacitive sensing interface circuit that has been designed and tested with a MEMS microphone and a capacitive micromachined ultrasonic transducer. Moreover, by using the charge programming technique, a designed floating-gate based large-scale field-programmable analog array (FPAA) containing a universal sensor interface sets the stage for reconfigurable smart sensory systems. Based on the same charge programming technique, a compact programmable analog radial-basis-function (RBF) based classifier and a resultant analog vector quantizer have been developed and tested. Measurement results have shown that the analog RBF-based classifier is at least two orders of magnitude more power-efficient than an equivalent digital processor. Furthermore, an adaptive bump circuit that can facilitate unsupervised learning in the analog domain has also been proposed. A projection neural network for a support vector machine, a powerful and more complicated binary classification algorithm, has also been proposed. This neural network is suitable for analog VLSI implementation and has been simulated and verified on the transistor level. These analog classifiers can be integrated at the interface to build smart sensory systems.

Bibliography :p.269-285. / xxii, 285 p. : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Describes a new method for describing asynchronous systems (free-flow asynchronism). The method is demonstrated through two applications ; a channel signalling system and amedo. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998