Diese Arbeit entwickelt eine Methode, Funktionalgleichungen der Art g(g(x))=f(x) bzw. g^n(x)=f(x) mit Hilfe neuronaler Netze zu lösen. Gesucht ist eine Funktion g(x), die mehrfach hintereinandergeschaltet genau einer gegebenen Funktion f(x) entspricht. Man nennt g=f^1/n eine iterative Wurzel oder fraktionale Iteration von f. Lösungen für g zu finden, stellt das inverse Problem der Iteration dar oder die Erweiterung der Wurzel- bzw. Potenzoperation auf die Funktionsalgebra. Geschlossene Ausdrücke für Funktionswurzeln einer gegebenen Funktion zu finden, ist in der Regel nicht möglich oder sehr schwer. Numerische Verfahren sind nicht in allgemeiner Form beschrieben oder als Software vorhanden. Ausgehend von der Fähigkeit eines neuronalen Netzes, speziell des mehrschichtigen Perzeptrons, durch Training eine gegebene Funktion f(x) zu approximieren, erlaubt eine spezielle Topologie des Netzes auch die Berechnung von fraktionalen Iterationen von f. Ein solches Netz besteht aus n identischen, hintereinandergeschalteten Teilnetzen, die, wenn das Gesamtnetz f approximiert, jedes für sich g = f^1/n annähern. Es ist lediglich beim Training des Netzes darauf zu achten, dass die korrespondierenden Gewichte aller Teilnetze den gleichen Wert annehmen. Dazu werden mehrere Verfahren entwickelt: Lernen nur im letzten Teilnetz und Kopieren der Gewichte auf die anderen Teile, Angleichen der Teilnetze durch Kopplungsfaktoren oder Einführung eines Fehlerterms, der Unterschiede in den Teilnetzen bestraft. Als weitere Näherungslösung wird ein iteriertes lineares Modell entwickelt, das durch ein herkömmliches neuronales Netz mit hoher Approximationsgüte für nichtlineare Zusammenhänge korrigiert wird. Als Anwendung ist konkret die Modellierung der Bandprofilentwicklung beim Warmwalzen von Stahlblech gegeben. Einige Zentimeter dicke Stahlblöcke werden in einer Walzstraße von mehreren gleichartigen, hintereinanderliegenden Walzgerüsten zu Blechen von wenigen Millimetern Dicke gewalzt. Neben der Dicke ist das Profil - der Dickenunterschied zwischen Bandmitte und Rand - eine wichtige Qualitätsgröße. Sie kann vor und hinter der Fertigstraße gemessen werden, aus technischen Gründen aber nicht zwischen den Walzgerüsten. Eine genaue Kenntnis ist jedoch aus produktionstechnischen Gründen wichtig. Der Stand der Technik ist die Berechnung dieser Zwischenprofile durch das wiederholte Durchrechnen eines mathematischen Modells des Walzvorganges für jedes Gerüst und eine ständige Anpassung von adaptiven Termen dieses Modells an die Messdaten. Es wurde gezeigt, dass mit einem adaptiven neuronalen Netz, das mit Eingangs- und Ausgangsprofil sowie allen vorhandenen Kenn- und Stellgrößen trainiert wird, die Vorausberechnung des Endprofils mit deutlich höherer Genauigkeit vorgenommen werden kann. Das Problem ist, dass dieses Netz die Übertragungsfunktion der gesamten Straße repräsentiert, Zwischenprofile können nicht ausgegeben werden. Daher wird der Versuch gemacht, beide Eigenschaften zu verbinden: Die genaue Endprofilmodellierung eines neuronalen Netzes wird kombiniert mit der Fähigkeit des iterierten Modells, Zwischenprofile zu berechnen. Dabei wird der in Form von Messdaten bekannte gesamte Prozess als iterierte Verknüpfung von technisch identischen Teilprozessen angesehen. Die Gewinnung eines Modells des Einzelprozesses entspricht damit der Berechnung der iterativen Wurzel des Gesamtprozesses.

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

One of the main tasks for an industrial robot is to move the end-effector in a predefined path with a specified velocity and acceleration. Different applications have different requirements of the performance. For some applications it is essential that the tracking error is extremely small, whereas other applications require a time optimal tracking. Independent of the application, the controller is a crucial part of the robot system. The most common controller configuration uses only measurements of the motor angular positions and velocities, instead of the position and velocity of the end-effector. The development of new cost optimised robots has introduced unwanted flexibilities in the joints and the links. The consequence is that it is no longer possible to get the desired performance and robustness by only measuring the motor angular positions.  This thesis investigates if it is possible to estimate the end-effector position using Bayesian estimation methods for state estimation, here represented by the extended Kalman filter and the particle filter. The arm-side information is provided by an accelerometer mounted at the end-effector. The measurements consist of the motor angular positions and the acceleration of the end-effector. In a simulation study on a realistic flexible industrial robot, the angular position performance is shown to be close to the fundamental Cramér-Rao lower bound. The methods are also verified in experiments on an ABB IRB4600 robot, where the dynamic performance of the position for the end-effector is significantly improved. There is no significant difference in performance between the different methods. Instead, execution time, model complexities and implementation issues have to be considered when choosing the method. The estimation performance depends strongly on the tuning of the filters and the accuracy of the models that are used. Therefore, a method for estimating the process noise covariance matrix is proposed. Moreover, sampling methods are analysed and a low-complexity analytical solution for the continuous-time update in the Kalman filter, that does not involve oversampling, is proposed.  The thesis also investigates two types of control problems. First, the norm-optimal iterative learning control (ILC) algorithm for linear systems is extended to an estimation-based norm-optimal ILC algorithm where the controlled variables are not directly available as measurements. The algorithm can also be applied to non-linear systems. The objective function in the optimisation problem is modified to incorporate not only the mean value of the estimated variable, but also information about the uncertainty of the estimate. Second, H∞ controllers are designed and analysed on a linear four-mass flexible joint model. It is shown that the control performance can be increased, without adding new measurements, compared to previous controllers. Measuring the end-effector acceleration increases the control performance even more. A non-linear model has to be used to describe the behaviour of a real flexible joint. An H∞-synthesis method for control of a flexible joint, with non-linear spring characteristic, is therefore proposed. / En av de viktigaste uppgifterna för en industrirobot är att förflytta verktyget i en fördefinierad bana med en specificerad hastighet och acceleration. Exempel på användningsområden för en industrirobot är bland annat bågsvetsning eller limning. För dessa typer av applikationer är det viktigt att banföljningsfelet är extremt litet, men även hastighetsprofilen måste följas så att det till exempel inte appliceras för mycket eller för lite lim. Andra användningsområden kan vara punktsvetsning av bilkarosser och paketering av olika varor. För dess applikationer är banföljningen inte det viktiga, istället kan till exempel en tidsoptimal banföljning krävas eller att svängningarna vid en inbromsning minimeras. Oberoende av applikationen är regulatorn en avgörande del av robotsystemet. Den vanligaste regulatorkonfigurationen använder bara mätningar av motorernas vinkelpositioner och -hastigheter, istället för positionen och hastigheten för verktyget, som är det man egentligen vill styra.  En del av utvecklingsarbetet för nya generationers robotar är att reducera kostnaden men samtidigt förbättra prestandan. Ett sätt att minska kostnaden kan till exempel vara att minska dimensionerna på länkarna eller köpa in billigare växellådor. Den här utvecklingen av kostnadsoptimerade robotar har infört oönskade flexibiliteter i leder och länkar. Det är därför inte längre möjligt att få den önskade prestandan och robustheten genom att bara mäta motorernas vinkelpositioner och -hastigheter. Istället krävs det omfattande matematiska modeller som beskriver dessa oönskade flexibiliteter. Dessa modeller kräver mycket arbete att dels ta fram men även för att identifiera parametrarna. Det finns automatiska metoder för att beräkna modellparametrarna men oftast krävs det en manuell justering för att få bra prestanda.  Den här avhandlingen undersöker möjligheterna att beräkna verktygspositionen med hjälp av bayesianska metoder för tillståndsskattning. De bayesianska skattningsmetoderna beräknar tillstånden för ett system iterativt. Med hjälp av en matematisk modell över systemet predikteras vad tillståndet ska vara vid nästa tidpunkt. Efter att mätningar av systemet vid den nya tidpunkten har genomförts justeras skattningen med hjälp av dessa mätningar. De metoder som har använts i avhandlingen är det så kallade extended Kalman filtret samt partikelfiltret.  Informationen på armsidan av växellådan ges av en accelerometer som är monterad på verktyget. Med hjälp av accelerationen för verktyget och motorernas vinkelpositioner kan en skattning av verktygspositionen beräknas. I en simuleringsstudie för en realistisk vek robot har det visats att skattningsprestandan ligger nära den teoretiska undre gränsen, känd som Raooch mätstörningar som påverkar roboten. För att underlätta trimningen så har en metod för att skatta processbrusets kovariansmatris föreslagits. En annan viktig del som påverkar prestandan är modellerna som används i filtren. Modellerna för en industrirobot är vanligtvis framtagna i kontinuerlig tid medan filtren använder modeller i diskret tid. För att minska felen som uppkommer då de tidskontinuerliga modellerna överförs till diskret tid har olika samplingsmetoder studerats. Vanligtvis används enkla metoder för att diskretisera vilket innebär problem med prestanda och stabilitet. För att hantera dessa problem införs översampling vilket innebär att tidsuppdateringen sker med en mycket kortare sampeltid än vad mätuppdateringen gör. För att undvika översampling kan det motsvarande tidskontinuerliga filtret användas för att prediktera tillstånden vid nästa diskreta tidpunkt. En analytisk lösning med låg beräkningskomplexitet till detta problem har föreslagits.  Vidare innehåller avhandlingen två typer av reglerproblem relaterade till industrirobotar. För det första har den så kallade norm-optimala iterative learning control styrlagen utökats till att hantera fallet då en skattning av den önskade reglerstorheten används istället för en mätning. Med hjälp av skattningen av systemets tillståndsvektor kan metoden nu även användas till olinjära system vilket inte är fallet med standardformuleringen. Den föreslagna metoden utökar målfunktionen i optimeringsproblemet till att innehålla inte bara väntevärdet av den skattade reglerstorheten utan även skattningsfelets kovariansmatris. Det innebär att om skattningsfelet är stort vid en viss tidpunkt ska den skattade reglerstorheten vid den tidpunkten inte påverka resultatet mycket eftersom det finns en stor osäkerhet i var den sanna reglerstorheten befinner sig.  För det andra har design och analys av H∞-regulatorer för en linjär modell av en vek robotled, som beskrivs med fyra massor, genomförts. Det visar sig att reglerprestandan kan förbättras, utan att lägga till fler mätningar än motorns vinkelposition, jämfört med tidigare utvärderade regulatorer. Genom att mäta verktygets acceleration kan prestandan förbättras ännu mer. Modellen över leden är i själva verket olinjär. För att hantera detta har en H∞-syntesmetod föreslagits som kan hantera olinjäriteten i modellen. / Vinnova Excellence Center LINK-SIC

The optimal steady-state control, and suboptimal adaptive control, of disturbed single-input-output systems are introduced, and the class of systems considered is defined. It is noted that the stochastic tracking problem divides into a deterministic tracking problem and a stochastic regulator problem; the solutions to these two problems are shown to be independent but formally similar. The continuous regulator problem is approached via both frequency and time domain methods: the former method is extended to cover unstable systems; the latter method is extended to include systems with input delay. The two regulators are shown to be externally equivalent. The frequency domain method is briefly described for discrete systems, and shown to include the minimum variance regulator of Åström and Peterka as a special case. Some systems which allow measurement noise to be treated as a system disturbance for the purposes of optimal controller design are investigated. A novel class of control laws is described in both continuous and discrete time; in the same way as the minimum variance regulator forms the basis of the self-tuning regulator of Åström and Wittenmark, these minimum variance controllers from the basis of a self-tuning controller. These minimum variance controllers have a number of advantages over the minimum-variance regulator, and are open to a number of interpretations including: a model following control law, and an extension of classical control laws to systems with delay. The optimality of this class of control laws is investigated, and analogies drawn with the previously considered k-step-ahead control laws; some examples are given to illustrate the method. An adaptive control law combining the above minimum variance controllers with a linear least-squares algorithm is proposed and shown to be self-tuning. These self-tuning controllers are only slightly more complex than the self-tuning regulator of Åström and Wittenmark, but have a number of advantages. Intuitive justification is given for the conjecture that some methods of Ljung, developed for the analysis of the self-tuning regulator, are applicable to the self-tuning controller. Simulated examples are given which compare and contrast the performance of the self-tuning controller with that of the self-tuning regulator. The first steps towards a quasi-continuous self-tuning controller are outlined.

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.

abstract: A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

This dissertation is a contribution toward developing all-optical binary delta sigma modulator (BDSM) [‎27] by changing its bistability to proteretic bistability in order to increase the modulator bandwidth frequency. An innovative delta sigma modulator called proteretic binary delta sigma modulator (PBDSM), which is optically compatible, is investigated theoretically and by modeling and simulation and its bandwidth superiority is proven. The time interval of PBDSM Δt calculation is driven and dynamic performance measure of PBDSM comparing to previous related work is computed, modeled and simulated. Modeling and simulations are based on Matlab-Simulink for ideal environment testing. The basic components of BDSM are the leaky integrator and the bi-stable device. Thus, the focus was on improving the bi-stable device to overcome the bandwidth limitation toward THz modulation frequency in optical domain. Consequently, proteresis bistability was investigated in semi-practical domain, using Matlab-Simulink function, for clear realization of its input-output characteristics and compared with the corresponding hysteresis bistability. The contribution in this research, regarding proteresis bi-stable device design, can be implemented in current technologies, both optical and electrical, of continuous-time delta sigma modulation. Furthermore, the new design showed capability and more flexibility in manipulating its output form and it showed more control on the way of conducting delta sigma modulator error correction.

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

abstract: Cigarette smoking remains a major global public health issue. This is partially due to the chronic and relapsing nature of tobacco use, which contributes to the approximately 90% quit attempt failure rate. The recent rise in mobile technologies has led to an increased ability to frequently measure smoking behaviors and related constructs over time, i.e., obtain intensive longitudinal data (ILD). Dynamical systems modeling and system identification methods from engineering offer a means to leverage ILD in order to better model dynamic smoking behaviors. In this dissertation, two sets of dynamical systems models are estimated using ILD from a smoking cessation clinical trial: one set describes cessation as a craving-mediated process; a second set was reverse-engineered and describes a psychological self-regulation process in which smoking activity regulates craving levels. The estimated expressions suggest that self-regulation more accurately describes cessation behavior change, and that the psychological self-regulator resembles a proportional-with-filter controller. In contrast to current clinical practice, adaptive smoking cessation interventions seek to personalize cessation treatment over time. An intervention of this nature generally reflects a control system with feedback and feedforward components, suggesting its design could benefit from a control systems engineering perspective. An adaptive intervention is designed in this dissertation in the form of a Hybrid Model Predictive Control (HMPC) decision algorithm. This algorithm assigns counseling, bupropion, and nicotine lozenges each day to promote tracking of target smoking and craving levels. Demonstrated through a diverse series of simulations, this HMPC-based intervention can aid a successful cessation attempt. Objective function weights and three-degree-of-freedom tuning parameters can be sensibly selected to achieve intervention performance goals despite strict clinical and operational constraints. Such tuning largely affects the rate at which peak bupropion and lozenge dosages are assigned; total post-quit smoking levels, craving offset, and other performance metrics are consequently affected. Overall, the interconnected nature of the smoking and craving controlled variables facilitate the controller's robust decision-making capabilities, even despite the presence of noise or plant-model mismatch. Altogether, this dissertation lays the conceptual and computational groundwork for future efforts to utilize engineering concepts to further study smoking behaviors and to optimize smoking cessation interventions. / Dissertation/Thesis / Doctoral Dissertation Bioengineering 2014

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.