This dissertation is about a new [delta sigma] analog-to-digital converter that offers enhanced quantization noise suppression at low oversampling ratios. This feature makes the converter attractive in applications where speed and resolution are simultaneously demanded. The converter exploits double-sampling for speed, and takes advantage of a new loop-filter to pin down passband quantization noise. A proto-type is fabricated in 0.18-[mu]m CMOS and tested. Results show that at 200-MS/s, the converter achieves an effective number of bits (ENOB) of 12.2-b in a 12.5-MHz signal band while consuming 89-mW from a 1.8-V supply. Using a common performance metric that takes into account of ENOB and signal bandwidth, the prototype outperforms all previously-reported IEEE switched-capacitor [delta sigma] modulators. / text

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / Electrical Engineering / Master / Master of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

No description available.

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Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The data distribution uses a Thiran all-pass filter to ensure stability and preserve the phase in the bandwidth of interest. Also, an online technique to compensate for the gain error mismatch in different channels and a skew error calibration technique for open loop configuration is proposed. For the over-all sampling rate of FS, i.e. bandwidth of FS/2 (according to Nyquist), this proposed technique allows calibration of skew error for input signal for most of the Nyquist bandwidth where frequency translation is applied to the input signal to provide calibration in the lower half of the Nyquist band. The simulation results for a 2-channel 14-bit current steering binary weighted TIDAC shows a substantial improvement in SNDR after calibration for input signals up to Nyquist frequency.

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