Operational transconductance amplifier and capacitor (OTA-C) filters have outstood among different types of filter due to high frequency and low power capabilities in the main stream digital CMOS technology. They have been widely used in computer hard disk drive (HDD) and wireless communication transceivers. OTA-C filters based on cascade and passive ladder simulation are well-known. However, multiple loop feedback (MLF) OTA-C filters which have certain advantages still have the scope for further research. So far there have been no explicit formulas for current-mode leapfrog (LF) filter design and performance evaluation of current-mode MLF OTA-C filters are still lacking. From application viewpoints, read channels for computer hard disk drives require very high frequency continuous-time filters. This automatically disqualifies active- RC/MOSFET-C filters and OTA-C filters become the only solution. In wireless communications, active-RC/MOSFET-C filters have been proved useful for mobile systems whose baseband frequency falls below a few MHz. However, for wireless LANs with the frequency of several tens of MHz, OTA-C filters are a strong candidate. Whilst in HDD read channels, cascaded OTA-C architectures have been most utilized and in wireless receivers, OTA-C structures based on ladder simulation have been popular, MLF OTA-C filters have not been practically used in either of the applications. This thesis describes some novel designs and applications of multiple loop feedback OTA-C filters with extensive CMOS simulations. Analogue filters for computer hard disk drive systems are first reviewed; the state of the art and design considerations are provided. Three VHF linear phase lowpass OTA-C filters are then designed, which include a seventh-order and a fifth-order current-mode filter based on the follow-the-leader-feedback (FLF) structure and a seventh-order voltage-mode filter using the inverse FLF (IFLF) configuration. These filters all have very low power consumption. The synthesis and design of general current-mode LF OTA-C filters are conducted next. Iterative design formulas for both all-pole and finite-zero functions are derived and explicit formulas for up to sixth-orders are given. These formulas are very easy to use for designing any type of characteristics. Subsequently, linear phase lowpass OTA-C filter design for HDD read channels using LF structures are investigated in details. A current-mode filter and a voltage-mode filter using the fifth-order LF structure are presented. The two filters can operate up to 800MHz and have very small passband phase ripple. Analogue filters for wireless communication baseband applications are also reviewed thoroughly in this thesis, where the design of a fourth-order current-mode FLF Butterworth lowpass OTA-C filter for multi-standard receivers is presented. Then two fifth-order current-mode elliptic lowpass OTA-C filters based on respective LF and FLF structures for wireless communication baseband are designed. Fifth-order voltage-mode IFLF and LF elliptic lowpass filters are also presented. All these MLF baseband filters designed can operate up to 40MHz to cover all important wireless and mobile standards. Simulations show that the LF structures have better dynamic range and stopband attenuation performances than the FLF and IFLF configurations.

Depuis 2002, différentes bandes de fréquences de plusieurs GHz dites « Ultra-Large Bande » (ULB), généralement comprises entre 3,1GHz et 10,6GHz, ont été libérées de par le monde pour la transmission d’informations sans fil. La largeur de ces bandes est telle qu’il devient envisageable d’utiliser des impulsions comme support de l’information en lieu et place d’une porteuse modulée comme cela est le cas habituellement. En effet, le spectre d’une impulsion étant inversement proportionnel à sa durée, une large plage de fréquences est requise pour la transmission d’informations via des impulsions. Cependant, il devient possible d’accroitre les débits en rapprochant les impulsions émises lorsque ceci est nécessaire, tout en offrant la possibilité d’éteindre les circuits et donc réduire la consommation lorsque deux impulsions sont suffisamment éloignées dans le temps.Le travail de recherche de cette thèse est dans ce contexte de proposer une structure d’émetteur impulsionnel reconfigurable disposant d’un contrôle suffisamment fin pour s’adapter aux différents canaux des standards IEEE 802.15.4 et 802.15.6 et ce, en n’utilisant que des circuits numériques pour les besoins des applications faibles coût. Pour cela, une étude théorique sur la mise en forme des impulsions requises est faite. Puis, il est question de la conception des différentes fonctions nécessaires à la mise en œuvre d’un émetteur impulsionnel reconfigurable, telles qu’un oscillateur contrôlé en tension pour la bande 3,1GHz-10,6GHz à démarrage rapide et que le circuit de mise en forme des oscillations associé. / Since 2002, various frequency bands of several GHz called "Ultra-WideBand" (UWB), generally between 3,1GHz and 10,6GHz, were liberalized in the world for wireless data transmission. The width of these bands is that it becomes possible to use pulses instead of a modulated carrier to transmit data. Indeed, as the spectrum of a pulse is inversely proportional to its duration, a wide range of frequencies is required for the transmission of information via pulses. However, it becomes possible to increase the rates by moving closer the emitted pulses when this is necessary, while providing the ability to switch off the circuits and thus reduce power consumption when two pulses are sufficiently far in time.To standardize the use of UWB frequency bands, standards such as IEEE 802.15.4 and 802.15.6 standards have emerged and have chosen to cut these frequency bands in channels of 500MHz and more. The aim of this thesis is also to propose a reconfigurable pulse transmitter structure with a fine enough control to address the different channels of IEEE 802.15.4 and 802.15.6 standard and, using only digital circuits to target low cost applications. For this, a theoretical study on the shaping of pulses required is made. Then it comes to the design of the various functions necessary for the implementation of a reconfigurable pulse transmitter, such as the implementation of a voltage controlled oscillator for 3,1GHz band-10,6GHz with quick start ability and the required oscillations shaping circuit.

La sophistication grandissante des dispositifs intelligents ultra-portatifs, tels que les smartphones ou les tablettes,crée un besoin d'amélioration des performances des organes de conversion de puissance.La tendance des technologies d'acheminement de puissance évolue progressivement vers une fréquence plus élevée, une meilleure densité d'intégration et une plus grande flexibilité dans les schémas d'asservissement. La modulation dynamique de tension est utilisée dans les circuits intégrés de gestion de puissances(DVS PMICs)des transmetteurs RF alors que la modulation DVFS est utilisée dans les PMICs dédiées au CPUs et GPUs. Des DCDC flexibles et fonctionnant à haute fréquence constituent aujourd'hui la solution principale en conjonction avec des régulateurs à faible marge de tension (LDO).L'évolution vers des solutions à base de HFDCDC de faibles dimensions pose un défi sérieux en matière de 1)stabilité des boucles d'asservissement,2)de complexité des architectures de contrôle imbriquant des machines d'état asynchrones pour gérer une large dynamique de puissance de sortie et 3)de portabilité de la solutions d'une technologie à une autre.Les solutions les plus courantes atteignent aujourd'hui une gamme de 2 à 6 Mhz de fréquence de découpage grâce à l'usage de contrôleurs à hystérésis qui souffrent de la difficulté à contenir la fréquence de découpage lors des variations de la tension ou du courant en charge.Nous avons voulu dans ce travail étendre l'usage des méthodes de conception et de modélisation conventionnelles comme le modèle petit signal moyen, dans une perspective de simplification et de création de modèles paramétriques. L'objectif étant de rendre la technique de compensation flexible et robuste aux variations de procédés de fabrication ou bien aux signaux parasités inhérents à la commutation de puissance.Certes, le modèle moyen petit signal, au demeurant bien traité dans la littérature, réponds amplement à la problématique de compensation des DCDCs notamment quand la stabilité s'appuie sur le zéro naturel à haute fréquence inhérent à la résistance série ESR de la capacité de sortie, mais les HFDCDC actuels utilisent des capacités MLCC ayant une très faible ESR et font appel à des techniques de compensation paramétriques imbriquant le schéma de compensation dans la génération même du rapport cyclique. La littérature existante sur le fonctionnement de la machine d'état, se contente d'une description simpliste de convertisseurs PWM/PFM mais ne donne que très peu d'éléments sur la gestion des opérations synchrones/asynchrones alternant PWM,PFM,écrêtage de courant, démarrage ou détection de défaillance. Dans ce travail, notre études est axée sur les deux aspects suivants:1)La modélisation paramétrique et la compensation de la boucle d'asservissement de HFDCDC et 2)la portabilité de la conception de la machine d'états du contrôleur notamment lorsqu'elle intègre des transitions complexes entre les modes.Dans la première section, nous avons développé un modèle petit signal moyen d'un convertisseur Buck asservi en mode courant-tension et nous l'avons analysé pour faire apparaitre les contributions proportionnelle, intégrale et dérivé dans la boucle. Nous avons démontré la possibilité d'utiliser le retour en courant pour assurer l'amortissement nécessaire et la stabilité de la boucle pour une large dynamique de variations des conditions de charge.Dans la seconde section, nous avons développé une architecture de machine d'états sophistiquée basé sur la méthode d'Huffman avec un effort substantiel d'abstraction que nous a permis de la concevoir en description RTL pour une gestion fiable du fonctionnement asynchrone et temps réel.Notre contribution théorique a fait l'objet d'une réalisation d'un PMIC de test comportant deux convertisseurs Buck cadencés à 12MHz en technologie BiCMOS 0.5um/0.18um. Les performances clefs obtenues sont:une surtension de 50mV pendant 2us suite à l'application d'un échelon de courant de 300mA. / The continuous sophistication of smart handheld devices such as smartphones and tablets creates an incremental need for improving the performances of the power conversion devices. The trend in power delivery migrates progressively to higher frequency, higher density of integration and flexibility of the control scheme. Dynamic Voltage Scaling Power Management ICs (DVS PMIC) are now systematically used for powering RF Transmitters and DVFS PMICS using Voltage and Frequency scaling are used for CPUs and GPUs. Flexible High frequency (HF) DC/DC converters in conjunction with low dropout LDOs constitute the main solution largely employed for such purposes. The migration toward high frequency/small size DCDC solutions creates serious challenges which are: 1) the stability of the feedback loop across a wide range of loading voltage and current conditions 2) The complexity of the control and often-non-synchronous state machine managing ultra large dynamics and bridging low power and high power operating modes, 3) The portability of the proposed solution across technology processes.The main stream solutions have so far reached the range of 2 to 6 MHz operation by employing systematically sliding mode or hysteretic converters that suffer from their variable operating frequency which creates EMI interferences and lead to integration problems relative to on-chip cross-talk between converters.In this work we aim at extend the use of traditional design and modeling techniques of power converters especially the average modeling technique by putting a particular care on the simplification of the theory and adjunction of flexible compensation techniques that don't require external components and that are less sensitive to process spread, or to high frequency substrate and supply noise conditions.The Small Signal Average Models, widely treated in the existing literature, might address most needs for system modeling and external compensation snubber design, especially when aiming on the high frequency natural zero of the output capacitor. However, HFDCDC converters today use small size MLCC capacitors with a very low ESR which require using alternative techniques mixing the compensation scheme with the duty cycle generation itself. The literature often provides a simplistic state machine description such as PWM/PFM operations but doesn't cover combined architectures of synchronous / non synchronous mode operations such as PWM, PFM, Current Limit, Boundary Clamp, Start, Transitional and finally Fault or Protection modes.In our work, we have focused our study on two main axes: 1) The parametric modeling and the loop compensation of HFDCDC and 2) the scalability of the control state machine and mode inter-operation. In the first part, we provided a detailed small signal averaged model of the “voltage and current mode buck converter” and we depicted it to emphasize and optimize the contributions of the Proportional, Integral and Derivative feedback loops. We demonstrated the ability to use the current feedback to damp and stabilize the converter with a wide variety of loading conditions (resistive or capacitive). In the second part, we provided architecture of the mode control state machine with different modes like the PWM, PFM, soft-start, current limit,… .The technique we have used is inspired by Huffman machine with a significant effort to make it abstract and scalable. The state machine is implemented using RTL coding based on a generic and scalable approach.The theoretical effort has been implemented inside a real PMIC test-chip carrying two 12MHz buck converters, each employing a voltage and current mode feedback loop. The chip has been realized in a 0.5um / 0.18um BiCMOS technology and tested through a dedicate Silicon validation platform able to test the analog, digital and power sections. The key performance obtained is a 50mV load transient undershoot / overshoot during 2us following a load step of 300mA (slope 0.3A/ns).

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-24T19:07:44Z No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-25T15:25:19Z (GMT) No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) / Made available in DSpace on 2017-04-25T15:25:19Z (GMT). No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) Previous issue date: 2013-11-29 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / A presente tese contribui para a análise, modelagem e projeto de controladores discretos de um sistema de geração fotovoltaico de 30 kWp conectado à rede elétrica sem filtros passivos. O conversor fonte de tensão (VSC) de interface é interligado a rede elétrica usando somente as indutâncias de dispersão de um banco de transformadores monofásicos como filtros harmônicos. Modelos discretos são desenvolvidos tanto para o lado CC quanto para o lado CA do conversor. A modelagem do lado CA foi feita nos sistemas de coordenadas αβ0 e dq0. Já a modelagem da dinâmica do lado CC foi feita no sistema de coordenadas dq de acordo com balanço de potência entre os terminais do VSC. Baseado nos modelos obtidos, duas estratégias básicas foram investigadas e discutidas para projetar os compensadores discretos usados para controlar as correntes sintetizadas por um sistema de geração fotovoltaico no modo de corrente. Resultados experimentais mostram que o uso apenas de controladores lineares, proporcional–integral (PI) e proporcional–ressonante (PR), sintonizados na componente fundamental não é suficiente para manter a qualidade das correntes geradas dentro dos padrões internacionais, devido a operação não linear do transformador de conexão. Para contornar o problema anterior duas soluções foram investigadas: (i) inclusão de múltiplos controladores ressonantes nas coordenadas αβ; e (ii) inclusão de um controlador repetitivo em paralelo com o controlador PI nas coordenadas dq. Resultados experimentais mostraram que ambas estratégias são adequadas para compensar as componentes harmônicas. Finalmente, foi proposta uma estratégia para controlar o conversor durante faltas assimétricas (Fault–ride through) e eliminar as oscilações no barramento CC durante condições de desbalanço. O controlador proposto é composto por uma parcela PI e duas parcelas ressonantes, as quais controlam as componentes média e oscilante, através da injeção correntes de sequencia positiva e negativa na rede, respectivamente. Resultados de simulação mostram que o controlador proposto é adequado para eliminar as oscilações no barramento CC sem prejudicar as estabilidade do sistema. / The current thesis contributes to the analysis, modelling and design of discrete time controllers which aim is to control a 30 kWp photovoltaic dispersed generation system connected to the electric grid without passive filters. In fact, the interface voltage– sourced converter (VSC) is connected to the grid using only the leakage inductance of a single–phase transformer bank as harmonic filters. Initially, discrete time models are developed to the converter’s DC–side as well as to the AC–side. The AC–side modelling is performed on αβ0 and dq0 coordinate systems. On the other hand, the DC–side dynamics are modeled on the dq frame according to the power balance between the converter’s terminals. Based on the models obtained, strategies to control the converter in the current mode control on the αβ and dq are developed and a methodology to design the controllers are addressed in details. Experimental results shown that only the use of linear controllers, proportional–integral (PI) and proportional–resonant (PR), tuned on the fundamental component are not sufficient to guarantee the quality of the generated currents according to international standards. This is due to the operation of the connection transformer in a nonlinear region. In order to overcome this drawback, two solutions are taken into account: (i) inclusion of several parallel resonant controller in αβ frame; and (ii) inclusion of a repetitive controller in parallel with the PI controller in the dq frame. Experimental results shown that both strategies are suitable to compensate the harmonic components on the output current. Finally, a strategy is proposed to control the system under asymmetrical faults (fault–ride through) and to mitigate the voltage oscillation on the DC–side during unbalance conditions. The proposed controller is composed of a PI part and two resonant parts, which controls the average and the oscillating voltage components, through the injection of positive and negative sequence currents into the grid, respectively. Simulation results shown that the proposed controller is suitable to mitigate the DC–side voltage oscillations without jeopardizing the system stability.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-26T12:14:24Z No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-26T12:26:45Z (GMT) No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) / Made available in DSpace on 2017-04-26T12:26:45Z (GMT). No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) Previous issue date: 2014-03-19 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação apresenta um estudo de conexão de um grupo gerador-diesel (GMG) trifásico em uma rede secundária de distribuição de energia elétrica. A integração do GMG é feita por uma unidade de processamento de energia (PPU) composta por um retificador trifásico não controlado conectado em série com um conversor fonte de tensão (VSC) modulado com uma estratégia de modulação por largura de pulso. O GMG pode operar de duas maneiras distintas: (i) modo standby (interligado) ou (ii) modo isolado. O conversor de saída da PPU pode ser controlado para injetar potência ativa na rede CA, ou como um filtro ativo de potência (FAP) compensando potência reativa e correntes harmônicas nos terminais das cargas. O VSC de interface é controlado no modo de corrente (CMC), sendo seus controladores projetados a partir de funções de transferência obtidas com o modelo matemático do sistema elétrico nas coordenadas dq0. Esses controladores são projetados com múltiplos integradores para garantir a qualidade da forma de onda da corrente injetada na rede CA. Dependendo do modo de operação é utilizada uma malha adicional para regular a tensão do barramento CC do conversor de interface. Para validar o modelo matemático e o algoritmo de controle são realizadas simulações digitais no programa PSIM. Resultados experimentais, obtidos com um protótipo de laboratório, cujos controladores foram implementados em um processador digital de sinais TMS320F28335 da Texas Instruments, são usados para validar as estratégias de controle propostas. / This dissertation presents a study about the connection of a three-phase Diesel Genset (DG) to a secondary distribution network. The integration of DG is done by a Power Processing Unit (PPU) composed of a three-phase rectifier connected in series with a Pulse Width Modulated Voltage Source Converter (VSC). The DG can operate in two distinct modes: (i) standby (interconnected) or (ii) islanding. The PPU’s output converter can be controlled to inject active power into AC electric grid, or as an Active Power Filter (APF), compensating the reactive power and harmonics currents at the load terminals. The VSC is controlled employing the current mode control (CMC), and its compensators are designed based on the electrical system transfer function in dq0 coordinates. Multiple rotating synchronous reference frame integrators (PI-MRI) are used to ensure the quality of the generated power. Depending on the operating mode, an additional loop is used to regulate the DC bus voltage. In order to validate the mathematical model and the control algorithm, digital simulations using PSIM are performed. Experimental results obtained with the prototype, which controllers were implemented in a TMS320F28335 of Texas Instruments are used to validate the proposed control strategies.

The diploma thesis deals about design of the ARC multifunctional filters using modern functional blocks. These active blocks are for example voltage feedback operational amplifiers (OAs), operational transconductance amplifiers (OTAs), current conveyors (CCIIs) or current mode analog multipliers, current feedback amplifiers (CFAs), integrated circuits with switched capacitors building blocks (SCs) and digital potentiometers. The filters are studied with ideal circuit models and models of third level (3) based on voltage controlled voltage sources, voltage controlled current sources etc. (analog behavioral modelling). The professional macromodels are used for example LT 1364 (Linear Technology), EL 2045 (Intersil), LT 1228 (Linear Technology), LM 13700 (National Semiconductor), EL 2082 (Intersil), AD 844 (Analog Devices) and others. The circuits of the designed filters are simulated in PSpice (OrCAD), parasite effects and effects of the real parts are studied. Tuning and electronic adjusting parameters these filters are discussed and controlled by simulation in PSpice. Properties some simulated circuits are compare with experimental results. In conclusion individual filters are discussed and compared their properties. The constructional details of the some filters are presented at the end of this work.

The present thesis is focused on all pass filters. The principle of all pass filters, their properties, the design of nth degree of these circuits will be analysed in succession and then some of functional blocks, by which these structures can be made, will be described. After that, the allpass filters will be designed and simulated in program OrCAD PSpice. First of all, the analysis will be performed with ideal components, then with real components. After that, the sensitivity and tolerance analysis will be made and the influence of parasite effects on circuit parameters will be examined. Once the experiments are finished, the design of Printed Circuit Board's (PCB) will be realized. Circuit showing the best parameters will be chosen for the design.

The dissertation deals with the design of fully differential frequency filters using the signal flow graphs. It presents the procedures for designing frequency filters, focusing on the active elements such as multiple-output current followers (MO-CF) and digitally adjustable current amplifiers (DACA), which work in a current mode. It is theoretically discussed the issue of designing the M-C graphs, which are the graphic analogy of voltage and current incidence matrices. There are also presented three designs of 2nd order frequency filter circuits using the indirect method of design by M-C graphs and one circuit design using the direct method. The results of each simulation and measurement are presented in a module frequency characteristics. Finally, there is a summary of M-C graphs characteristics and applicability.