MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF).

Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers’ relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.

Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

Depuis 2002, différentes bandes de fréquences de plusieurs GHz dites « Ultra-Large Bande » (ULB), généralement comprises entre 3,1GHz et 10,6GHz, ont été libérées de par le monde pour la transmission d’informations sans fil. La largeur de ces bandes est telle qu’il devient envisageable d’utiliser des impulsions comme support de l’information en lieu et place d’une porteuse modulée comme cela est le cas habituellement. En effet, le spectre d’une impulsion étant inversement proportionnel à sa durée, une large plage de fréquences est requise pour la transmission d’informations via des impulsions. Cependant, il devient possible d’accroitre les débits en rapprochant les impulsions émises lorsque ceci est nécessaire, tout en offrant la possibilité d’éteindre les circuits et donc réduire la consommation lorsque deux impulsions sont suffisamment éloignées dans le temps.Le travail de recherche de cette thèse est dans ce contexte de proposer une structure d’émetteur impulsionnel reconfigurable disposant d’un contrôle suffisamment fin pour s’adapter aux différents canaux des standards IEEE 802.15.4 et 802.15.6 et ce, en n’utilisant que des circuits numériques pour les besoins des applications faibles coût. Pour cela, une étude théorique sur la mise en forme des impulsions requises est faite. Puis, il est question de la conception des différentes fonctions nécessaires à la mise en œuvre d’un émetteur impulsionnel reconfigurable, telles qu’un oscillateur contrôlé en tension pour la bande 3,1GHz-10,6GHz à démarrage rapide et que le circuit de mise en forme des oscillations associé. / Since 2002, various frequency bands of several GHz called "Ultra-WideBand" (UWB), generally between 3,1GHz and 10,6GHz, were liberalized in the world for wireless data transmission. The width of these bands is that it becomes possible to use pulses instead of a modulated carrier to transmit data. Indeed, as the spectrum of a pulse is inversely proportional to its duration, a wide range of frequencies is required for the transmission of information via pulses. However, it becomes possible to increase the rates by moving closer the emitted pulses when this is necessary, while providing the ability to switch off the circuits and thus reduce power consumption when two pulses are sufficiently far in time.To standardize the use of UWB frequency bands, standards such as IEEE 802.15.4 and 802.15.6 standards have emerged and have chosen to cut these frequency bands in channels of 500MHz and more. The aim of this thesis is also to propose a reconfigurable pulse transmitter structure with a fine enough control to address the different channels of IEEE 802.15.4 and 802.15.6 standard and, using only digital circuits to target low cost applications. For this, a theoretical study on the shaping of pulses required is made. Then it comes to the design of the various functions necessary for the implementation of a reconfigurable pulse transmitter, such as the implementation of a voltage controlled oscillator for 3,1GHz band-10,6GHz with quick start ability and the required oscillations shaping circuit.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.