Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / This work presents the study and implementation of an ac-dc Ćuk converter based on the three state switching cells applied in charger stations for electric vehicles. This converter has, as main characteristics, reduction of conducting power losses in the semiconductors, a single stage topology and current source behavior for both input and output terminals. As drawbacks, the topology presents: the voltage across the semiconductors is equal to the sum of the input and the output voltages, and a difference between the current values through the semiconductors caused by an inappropriate layout of the power prototypes or by a lack of symmetry between the control signals. The analysis of the converter is made through the qualitative and quantitative studies, beyond the analysis of the semiconductor losses which are presented as well. The current and voltage of the battery are controlled by the average current mode technique, which consist in a fast current control loop if compared with the terminals battery voltage control loop. The topology is design for 1 kW output power, 220 V in input voltage and 162 V in the output terminals (12 batteries in series connection). Experimental results for resistive load, as well batteries, are shown in order to verify the functionalities of the topology and its characteristics. / Este trabalho apresenta o estudo e desenvolvimento de um conversor ca-cc Ćuk baseado na cÃlula de comutaÃÃo trÃs estados para aplicaÃÃo em carregadores de baterias para veÃculos elÃtricos. As principais caracterÃsticas deste conversor sÃo: a reduÃÃo das perdas por conduÃÃo nos interruptores controlados, um Ãnico estÃgio de processamento de potÃncia e caracterÃstica de fonte de corrente na entrada e na saÃda. Como inconvenientes a topologia apresenta: a tensÃo sobre os semicondutores igual à soma das tensÃes de entrada e saÃda e o desequilÃbrio de corrente atravÃs dos componentes quando hà assimetria no layout da placa de potÃncia ou nos sinais de comando dos interruptores. Um estudo teÃrico à realizado atravÃs das anÃlises qualitativa e quantitativa, alÃm das anÃlises do processo de comutaÃÃo e das perdas nos componentes do conversor. Para controlar o fluxo de potÃncia da rede elÃtrica para as baterias à utilizada a estratÃgia de controle modo corrente mÃdia, sendo que, a mesma apresenta uma malha de corrente rÃpida que monitora a corrente de entrada e uma malha de tensÃo lenta que supervisiona a tensÃo sobre os terminais da bateria. Neste trabalho à realizado o projeto do carregador de baterias para aplicaÃÃo em veÃculos elÃtricos com 1 kW de potÃncia, tensÃo de entrada eficaz de 220 V e tensÃo de saÃda de 162 V, correspondente a 12 baterias conectadas em sÃrie. Um protÃtipo com as especificaÃÃes indicadas foi construÃdo e testado experimentalmente em laboratÃrio e os resultados de simulaÃÃo e experimentais obtidos sÃo utilizados para validar a anÃlise teÃrica e o projeto realizado. Foram realizados testes com carga puramente resistiva e em seguida com um banco de baterias, que comprovaram o funcionamento da topologia.

Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Limited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor. This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across different supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 μm technology and 1.8 V nominal supply. The proposed oscillator manages to achieve a frequency standard deviation across all PVT variations less than ±6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 μW. The layout of the oscillator's core area takes up 0.003 mm2.

Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

In this thesis, a test system is designed and implemented in order to evaluate the basic electrical performance and determine the parameters of ultracapacitors (UC). The implemented UC test system is based on power electronics converters and it is capable of charging and discharging the UC under test with predetermined current profiles. The charging operation is provided by a configuration involving the AC utility grid, a step-down transformer, a diode bridge, and a DC bus filter capacitor followed by a step-down DC-DC converter. The energy stored in the UC under test, as a result of the charging operation, is discharged to a resistor bank through a step-up DC-DC converter and a DC chopper structure. The charging and discharging current applied to the UC under test is provided by means of current mode control of power electronics converters. The control mechanism of the power electronics converters and the transition operations between the charging and discharging phases of the test system is realized via a microcontroller supported hardware structure. In the scope of the thesis study, a UC module composed of five serially connected UC cells is constructed. Constant current and constant power tests are applied to the constructed UC module. The performance of the implemented UC test system is investigated by means of computer simulations and experimental results. Further, basic electrical behaviour of the constructed UC module is evaluated and the parameters are extracted experimentally.

In this thesis a two-stage AC/DC/DC power converter is designed and implemented. The AC/DC input stage of the converter consists of the two&amp / #8211 / phase interleaved boost topology employing the average current mode control principle. The output stage consists of a zero voltage switching phase shifted full bridge (ZVS&amp / #8211 / PS&amp / #8211 / FB) DC/DC converter. For the input stage, main design goals are obtaining high input power factor, low input current distortion, and well regulated output dc voltage, and obtaining these attributes in a power converter with high power density. For the input stage, the interleaved structure has been chosen in order to obtain reduced line current ripple and EMI, reduced power component stresses, and improved power density. The control of the pre&amp / #8211 / regulator is provided by utilizing a new commercial monolithic integrated circuit, which provides interleaved continuous conduction mode power factor correction (PFC). The output stage is formed by utilizing the available prototype hardware of a ZVS&amp / #8211 / PS&amp / #8211 / FB DC/DC converter and mainly the system integration and controller design and implementation studies have been conducted. The converter small signal model is derived and utilizing its transfer function and employing voltage loop control, the output voltage regulator has been designed. The output voltage controller is implemented utilizing a digital signal processor (DSP). Integrating the AC/DC preregulator and DC/DC converter, a laboratory AC/DC/DC converter system with high overall performance has been obtained. The overall system performance has been verified via computer simulations and experimental results obtained from laboratory prototype.

In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.

Αντικείμενο της παρούσας Ειδικής Επιστημονικής Εργασίας είναι η μελέτη, σχεδίαση, εξομοίωση και φυσική σχεδίαση ενός αναλογικού μιγαδικού ζωνοδιαβατού φίλτρου 6ης τάξης. Βασικές δομικές μονάδες του φίλτρου είναι ενισχυτές ρεύματος οι οποίοι χρησιμοποιούν τη βαθμίδα “Flipped Voltage Follower”. Με τη συγκεκριμένη βαθμίδα είναι εφικτή η σχεδίαση όλων των επιμέρους κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας-χαμηλής κατανάλωσης ισχύος. / The subject of this master thesis is the design, simulation and physical layout of a 6th order analog complex bandpass filter. The filter is constructed by current mirrors which are utilizing the cell "Fliped Voltage Follower". Thus, all of the circuits offer the benefit of operating in low-voltage/low-power environment.

nÃo hà / O presente trabalho propÃe o estudo do conversor boost CC-CC de alto ganho de tensÃo baseado na cÃlula de comutaÃÃo de trÃs estados e nas cÃlulas multiplicadoras de tensÃo (mc). Este trabalho investiga um modelo matemÃtico para o citado conversor. A anÃlise proposta à baseada na ferramenta âmodelagem do interruptor PWM para conversores CC-CCâ. O modelo deve ser encontrado por uma simples inspeÃÃo do circuito do conversor. Deve ser possÃvel aplicÃ-lo para realizar diversas anÃlises, como em regime permanente, regime transitÃria e anÃlise de pequenos sinais por meio de um uma abordagem unificada. Considerando um dado nÃmero de cÃlulas multiplicadoras de tensÃo, duas situaÃÃes sÃo analisadas com esta ferramenta: operaÃÃo com uma Ãnica cÃlula multiplicadora de tensÃo (mc=1) e vÃrias cÃlulas multiplicadoras de tensÃo (mc> 1). O mÃtodo proposto à validado por simulaÃÃes e à verificada sua efetividade. AlÃm disso, à analisado neste trabalho o controle modo corrente mÃdia convencional, o qual à aplicado em uma das configuraÃÃes em estudo. O rendimento do conversor e a efetividade do controlador proposto sÃo demonstrados por resultados experimentais para um protÃtipo do laboratÃrio de 1 kW. / The present work proposes the study of the boost converter based on three-state switching cell and voltage multipliers cells (mc). A mathematical model of the aforementioned converter is investigated here. The proposed analysis is based on the tool named âPWM-Switch Modeling of DC-DC Convertersâ. The model must be found by a simple inspection of the converterâs circuit. It is possible to apply such model in order to realize various analyses such as steady-state, transient, and small-signal analysis in a single and same model. Considering the number of voltage multipliers cells (mc), two situations are analyzed: operation with a single multiplier cell (mc=1) and operation with multiple voltage multiplier cells (mc>1).The proposed method was validated through simulations and its effectiveness was verified. In addition to this, conventional average current mode control is also applied to one of the studied configurations. The performance of the converter and the effectiveness of the proposed controller are demonstrated by experimental results obtained from a 1-kW laboratory prototype.

The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synthetic inductor is made with the current conveyors in the first case and with the current operational amplifiers with single input and differential output in the second case. This method advantage is relatively simple design and disadvantage is great quantity of active functional blocks. Active filters based on passive frequency ladder 3rd order filter while only one floating inductor is connected, are designed with circuit equation method. In the first design differential input / output current followers are used and in the second case current-differencing buffered amplifiers are used. This method benefits by smaller active blocks number and disadvantage is more complex design of the active filter. Active filter based on passive prototype of low-pass 3rd order filter with two floating inductors is designed with Bruton transformation method. Final active filter uses current operational amplifiers with single input and differential output which together with other passive elements replace frequency depending negative resistor, which arise after previous Bruton transform. This method usage is advantageous if the design consists of larger quantity of inductors and less number of capacitors. High-pass 2nd order filter is simulated by tolerance and parametrical analyses. Physical realisation utilising current feedback operational amplifier which substitute commercially hardly accessible current conveyors is subsequently made. Measurements of constructed active filter show that additional modifications, which allow better amplitude frequency characteristics conformity, are necessary.