The diploma thesis deals with analysis, validation, measurement of parameters of the commercially available current multiplies (namely the EL2082 and EL4083) and their applications in practice. Control analysis are carried out in OrCAD PSpice program and compared with values from datasheets. Control analysis are focused on AC and DC characteristics of these active blocks. There are discusses the input impedance, the output impedance, the current gain and the possibility of electronic adjusting. The parameters of the elements were verified by measurements. Proposals for circuit applications (selective circuit, oscillator, frequency filter) with EL2082 and EL4083 are presented and analyzed in the program OrCAD. Three oscillator circuit designs are experimentally tested and the results are compared with the theoretical expectations and simulations in OrCAD. The possibility of electronic control for oscillators is examined. Also the sensitivity and the tolerance analysis are carried out. The constructional details of oscillators are presented at the end of this work.

The master thesis deals with designs of the single-ended and the fully-differential secondorder frequency filters with adjustable parameters. This filters operate in the current mode where main element is the current amplifier DACA (Digitally Adjustable Current Amplifier). The first part describes basic behaviour of frequency filters and distribution according to filter funcion, used parts and structure. The second part of thesis describes the design of the frequency filters by the M-C signal-flow graphs and the transformating single-ended structures to the fully-differential forms. The next part deals with properties of the active elements and their simulation models. The following part describe six circuits of the frequency filters with adjustable parameters and their simulations. Four simulation models with different properties were used for simulating of the DACA in the each circuits. The last part deals with the practical design and measurement of the selected frequency filters.

This master’s thesis deals with designing of fully-differential current-mode frequency filters using signal-flow graphs method. The first part is focused on a general description of frequency filters, its function and division. Active elements that create these frequency filters, such as multi-output current follower (MO-CF), balanced or multi-output transconductance amplifier (BOTA, MOTA) and digitally adjustace current amplifier (DACA) are described in the following part. Next, problems and various techniques of designing such filters are discussed on a theoretic basis. In the remaining part of the thesis there are six circuits of frequency filters described in detail; these connections are then transferred of passive elements to a proposed connections, with the assistance of a so-called reflection. Calculations of passive form are stated, as well as results of simulations, where nondifferential and differential variations of these designed frequency filters are compared. Finaly, it has been selected some variants of designs, which has been manufactured, then measured out and resulet has been compare between each other.

This diploma thesis is concentrated to fully differential and non-differential fractional-order filters with active elements. It describes how we can obtain fractional-order fully-differential filters design from non-differential design, thesis describes realization in OrCad program and simulation of this project. The first part of the thesis concerns theoretical analysis of frequency filters, active elements and fractional-order filters. The second part of the thesis includes designs of filters and simulations of differential structures and rest of non-differential structures simulation. The following part of the thesis concerns practical realization and experimental measurment of differential fractional-order filter. In the last part of this project, thesis evaluates all results which were revealed in our simulations and experimental measurment.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

No description available.

Η παρούσα διδακτορική διατριβή εστίασε το ενδιαφέρον της στην διερεύνηση των αναλογικών ολοκληρωμένων φίλτρων της κατηγορίας ELIN εξωτερικά γραμμικά, εσωτερικά μη-γραμμικά. Συγκεκριμένα μελετήθηκαν και σχεδιάστηκαν, νέες δομές φίλτρων συμπίεσης-αποσυμπίεσης του προς επεξεργασία σήματος στο πεδίο του υπερβολικού ημιτόνου χαμηλής τάσης τροφοδοσίας. Η γοργή ανάπτυξη της μικροηλεκτρονικής στην υλοποίηση συστημάτων υψηλής αξιοπιστίας και απόδοσης μικρού βάρους και όγκου όπως φορητών ηλεκτρονικών πολυμέσων, επικοινωνιών, βιοϊατρικών συσκευών, ωθεί στην σχεδίαση των ολοκληρωμένων κυκλωμάτων που τα απαρτίζουν με μειωμένη κατανάλωση ισχύος και κατ’ επέκταση χαμηλής τάσης τροφοδοσίας. Σ’ ένα ολοκληρωμένο κύκλωμα η ενσωμάτωση αναλογικών και ψηφιακών κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας, ώστε το κόστος των διατάξεων να διατηρείται χαμηλό, επηρεάζει άμεσα την απόδοση του αναλογικού τμήματος, προτάσσοντας την ανάγκη για νέες αρχιτεκτονικές σχεδίασης του. Οι διατάξεις των αναλογικών φίλτρων αποτελούν συχνά δομικό στοιχείο των ολοκληρωμένων κυκλωμάτων και η διερεύνηση τους για την επίτευξη μεγάλης δυναμικής περιοχής, ηλεκτρονική ρύθμισης της απόκρισης συχνότητας και ταυτόχρονα χαμηλής κατανάλωσης ισχύος, έχει απασχολήσει αρκετά το ενδιαφέρον της ερευνητικής κοινότητας. Προτείνεται αρχικά η συστηματική σχεδίαση φίλτρων υψηλής τάξης στο πεδίο του υπερβολικού ημιτόνου, αποσκοπώντας στη βελτίωση της διαδικασίας υλοποίησης τους, με χρήση ήδη υπαρχουσών μη-γραμμικών διαγωγών υπερβολικού ημιτόνου, συνημίτονου. Η συμπίεση-αποσυμπίεση του προς επεξεργασία σήματος επιτυγχάνεται με την κατάλληλη τοποθέτηση συμπληρωματικών τελεστών ενώ ταυτόχρονα διατηρείται γραμμική η συνολική συμπεριφορά των διατάξεων. Με γνώμονα την εφαρμογή τους σε βιοϊατρικές συσκευές, εξομοιώνεται με δύο διαφορετικούς τρόπους φίλτρο 3ης τάξης leapfrog με συχνότητα αποκοπής 10Hz και τα αποτελέσματα που προκύπτουν συγκρίνονται με αντίστοιχο γραμμικής συμπεριφοράς. Στην συνέχεια, υλοποιείται η σχεδίαση BiCMOS φίλτρων οποιασδήποτε τάξης, δομημένα από μη-γραμμικούς διαγωγούς υπερβολικού ημιτόνου με δυνατότητα λειτουργίας σε υψηλές συχνότητες και σε χαμηλή τάση τροφοδοσίας. Επιλέγονται οι μέθοδοι του γραμμικού μετασχηματισμού, λειτουργικής και τοπολογικής εξομοίωσης ενός πρωτότυπου ελλειπτικού βαθυπερατού 3ης τάξης με συχνότητα αποκοπής 0.5 kHz και κυμάτωση στην ζώνη διέλευσης 0.5dB. Ακολουθεί ανάλυση και σύγκριση των αποτελεσμάτων που προκύπτουν στο περιβάλλον Analog Virtuoso της Cadence Software, της τεχνολογίας AMS CMOS S35 0.35μm, μεταξύ των φίλτρων στο πεδίο του υπερβολικού ημιτόνου καθώς και με αντίστοιχες διατάξεις στο πεδίο του λογαρίθμου τάξης-ΑΒ και (OTA)-C στο γραμμικό χώρο. Προτείνεται ακόμη, η BiCMOS σχεδίαση γενικευμένων φίλτρων 2ης τάξης απλής εισόδου-πολλαπλών εξόδων και πολλαπλής εισόδου-απλής εξόδου, με δυνατότητα λειτουργίας σε περιβάλλον χαμηλής τάσης τροφοδοσίας, ηλεκτρονικής ρύθμισης της συχνότητας αποκοπής ω0 του συντελεστή ποιότητας Q και της ορθογώνιας μεταβολής μεταξύ των. Από την εξομοίωση τους πρόκυψε ότι είναι ενεργειακά αποδοτικότερη η υλοποίηση τους συγκρινόμενα με αντίστοιχα στο πεδίο του λογαρίθμου. Τέλος, στα πλαίσια υλοποίησης βιοϊατρικών εφαρμογών προτείνεται η σχεδίαση ενός μη-γραμμικού τελεστή ενέργειας στο πεδίο του υπερβολικού ημιτόνου για την ανίχνευση αιχμών δραστηριότητας σε νευρωνικά δίκτυα με τάση τροφοδοσίας 0.5V. Ο μη-γραμμικός διαγωγός υπερβολικού ημιτόνου, του οποίου ο διαγραμμικός βρόγχος αποτελείται από (pMOS) τρανζίστορ δομεί τους διαφοριστές και πολλαπλασιαστές τεσσάρων τεταρτημορίων τάξης-ΑΒ που απαρτίζουν την διάταξη. Εξομοιώνεται, κάνοντας χρήση CMOS τρανζίστορ της τεχνολογίας TSMC 130 nm, στο περιβάλλον Analog Virtuoso της Cadence Software και συγκρινόμενος με ήδη υπάρχουσες διατάξεις, παρουσιάζει την μικρότερη κατανάλωση ισχύος. / This present Ph.D dissertation is focused its interest on the design of low voltage analog integrated circuits. Companding (compressing-expanding) systems are Externally Linear, Internally Non-linear (ELIN) processors with potential for low-voltage operation capability. In this direction novel topologies of companding filters in the Sinh-Domain are introduced. Τhe radical technological developments of microelectronics in the systems implementation with high reliability and performance, such as portable electronic devices for multimedia, communications and biomedical systems, demand the design of integrated circuits with reduced power consumption and thus low voltage supply. Integration of analog and digital circuits of systems-on-chip – (SoC) in order to be kept the low cost, directly affects the performance of the analog section, pointing forward the need for novel architectural design. One of the basic building blocks for circuit design is analog filters and their investigation in order to achieved large dynamic range, electronic tuning capability of their frequency characteristics which has gained a significant research effort toward these goals. At first, a new systematic method for designing Sinh-Domain filters is introduced. The proposed method offers the benefits of facilitating the design procedure of high-order Sinh-Domain filters using already introduced building blocks and of the absence of any restriction concerning the type and/or the order of the realized filter function. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh-Domain. In order to demonstrate the validity of the proposed systematic method, 3rd order leapfrog low-pass filter with a cut-off frequency at 10Hz which is typical for biomedical applications, has been realized following two alternative approaches and, also, a comparison has been performed among them and a conventional linear filter where the most important performance factors have been taken into account. Continuing, novel BiCMOS sinh-domain filter topologies, derived according to operational emulation, component substitution techniques and Linear Transformation of the corresponding 3rd-order passive prototype filters, with a cut-off frequency at 0.5 kHz and pass-band ripple 0.5dB, is proposed. This has been achieved by utilizing BiCMOS nonlinear ransconductor cells into the sinh domain. An attractive benefit of the proposed filter topologies is their capability for operating in high frequencies and a low-voltage environment. The performance of a leapfrog sinh-domain filter has been compared, using the Analog Design Environment of the Cadence software using AMS CMOS S35 0.35μm, with those of the corresponding log-domain and operational ransconductance amplifier (OTA)-C filters. Furthermore, the design of a family of Sinh-Domain universal biquad filters are introduced offering the benefits of low-voltage operation and, simultaneously, power efficient realizations in comparison with the corresponding already proposed biquads. Also, they have the capability for orthogonal adjustment between the resonance frequency and Q factor of the filter and these parameters could be also electronically adjusted through appropriate dc currents. Thus, they could be considered as attractive blocks for realizing high-performance analog signal processing systems. Finally, a Sinh-Domain topology for realizing the Non Linear Energy Operator (NEO) is introduced. For this purpose, a novel Sinh-Domain differentiator is proposed which offers the benefits of ultra low-voltage operation capability and electronic tuning of the realized time-constant. The whole system is also constructed from a four-quadrant current multiplier, realized by employing appropriately configured non-linear transconductors. Considering a single power supply voltage of 0.5V, the behavior of the proposed Sinh-Domain NEO realization has been simulated using the Analog Design Environment of the Cadence software using TSMC 130 nm design hit.

This dissertation is aimed at the development of a current mode instrumentation amplifier (CMIA) with a high common mode input range. This characteristic is obtained due to the rail-to-rail operational amplifiers (opamps). These opamps are built with rail-to-rail differential amplifiers as input stages, and with cascode-based output stages, which are able to copy its current by adding identical branches and connecting their gates without the voltage degradation as the known CMIA topologies. The main contribution of this work is the development of a rail-to-rail current mode instrumentation amplifier, analyzing the pros and cons of this topology. The functionality of the proposed topology is shown through measured results of a manufactured integrated circuit. This first prototype, although it was operated in a large input common mode range, presented insufficient values of CMRR (Common Mode Rejection Ratio) and VOS (Offset voltage). These two characteristics were studied and modeled, the instrumentation amplifier was re-designed, and simulated results demonstrate important improvements. / Esta dissertação tem como objetivo o desenvolvimento de um amplificador de instrumentação em modo corrente com uma ampla faixa de entrada em modo comum. Esta característica é obtida graças ao emprego de estágios de amplificação rail-to-rail na entrada e a geração do sinal de saída através do espelhamento da corrente diretamente dos gates dos transistores do estágio ao invés da alternativa clássica, onde espelhos são ligados em série e degradam a excursão do sinal de saída. Com esta proposta, é possível a implementação de ampops com entrada e saída rail-to-rail. A principal contribuição deste trabalho é analisar as vantagens e desvantagens da utilização destas soluções na implementação de um amplificador de instrumentação com entrada rail-to-rail. A funcionalidade da topologia proposta é demonstrada através dos resultados medidos de um circuito integrado fabricado. Este primeiro protótipo, apesar do bom funcionamento em toda a faixa de entrada em modo comum, apresentou valores insatisfatórios de CMRR (Common Mode Rejection Ratio) e de VOS (Tensão de offset), o que levou a um aprofundamento no estudo e modelagem destas características. A partir disto, o circuito foi re-projetado e os resultados de simulação demonstram melhorias bastante significativas em suas características.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-20T13:39:03Z No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-20T14:45:37Z (GMT) No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) / Made available in DSpace on 2017-04-20T14:45:37Z (GMT). No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) Previous issue date: 2011-04-29 / Esta dissertação apresenta uma estratégia de controle para sistemas de geração fotovoltaicos, de único estágio, trifásicos, conectados à rede elétrica de distribuição. São desenvolvidos modelos matemáticos para representar as características dinâmicas dos painéis fotovoltaicos, do conversor fonte de tensão (VSC -“Voltage Source Converter”) e da rede de distribuição. A modelagem do sistema de geração disperso (SGD) é feita no sistema de coordenadas síncrono (dq), fornecendo um sistema de equações diferenciais que pode ser usado para descrever o comportamento dinâmico do sistema quando as tensões da rede estão equilibradas ou desequilibradas. O conversor é controlado no modo de corrente, através da estratégia de modulação vetorial (Space Vector Modulation - SVM). São projetadas duas malhas de controle em cascata para controlar o conversor estático. A malha interna controla a corrente injetada na rede enquanto que a externa controla a tensão no barramento CC do conversor. O controle da tensão CC permite rastrear o ponto de máxima potência do painel PV além de controlar a quantidade de potência ativa injetada na rede CA. Um método ativo de detecção de ilhamento baseado na injeção de corrente de sequência negativa é incorporado ao sistema de controle. Resultados de simulações digitais obtidos com o programa ATP (Alternative Transient Program ) são utilizados para validar os modelos matemáticos e as estratégias de controle. Finalmente, um protótipo experimental de pequena escala é montado em laboratório. Todo o sistema de controle do protótipo experimental foi implementado no DSP TMS320F28212. Os resultados obtidos demonstram o funcionamento do sistema e podem ser usados para validar a estratégia de controle utilizada. / This dissertation presents a control strategy for a single-stage, three-phase, photovoltaic systems to be connected to a distribution network. Mathematical models are developed to represent the dynamic characteristics of the photovoltaic panels, the voltage-source converter (VSC) and the distribution network. The modeling of the dispersed generation system (DGS) is done in the synchronous reference frame (dq), providing a system of differential equations that describes the dynamic behavior of the system when the network voltages are balanced or unbalanced. The converter is controlled in current mode through the space vector modulation (SVM) strategy. Two control loops are designed to control the static converter. The inner loop controls the injected current into the network while the external loop controls the converter DC bus voltage. The DC voltage regulator allows to track the PV maximum power point and to control the active power injected into the AC grid. An active islanding detection method based on negative-sequence current injection is incorporated into the control system. Digital simulations results obtained with Alternative Transients Program (ATP) is used to validate the mathematical models and the control strategies. Finally, a small-scale experimental prototype is implemented in the laboratory. The whole control system of the experimental prototype was programmed in DSP TMS320F2812 of Texas Instruments. The results demonstrate that the operation of the system can be used to validate the applied control strategy.

Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area efficient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Defined Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based differential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in difficult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, fine time resolution, small die size and low power consumption simultaneously. The measured time-difference error is less than 50 ps at 1.2 V, enabling a resolution of 3 mm/kHz frequency shift. 4 A bio-sensor array for dielectric constant measurement: A CMOS on-chip sensor is presented to measure the dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of a current controlled os¬cillator (CCO) upon the change of the sensor capacitance when exposed to the liquid. The CCO is embedded in an open-loop frequency synthesizer to convert the frequency change into voltage, which can be digitized using an off-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. 5 Integrated Temperature Sensor for thermal management: An integrated analog temper¬ature sensor which operates with simple, low-cost one-point calibration is proposed. A frequency domain technique to measure the on-chip silicon surface temperature, was used to measure the effects of temperature on the stability of a frequency synthesizer. The temperature to voltage conversion is achieved in two steps i.e. temperature to frequency, followed by frequency to voltage conversion. The output voltage can be used to com¬pensate the temperature dependent errors in the high frequency circuits, thereby reduc¬ing the performance degradation due to thermal gradient. Furthermore, a temperature measurement-based on-chip self test technique to measure the 3 dB bandwidth and the central frequency of common radio frequency circuits, was developed. This technique shows promise in performing online monitoring and temperature compensation of RF circuits.