L’objectif de cette étude est d’améliorer les performances des transformateurs piézoélectriques en terme de courant de sortie et de puissance pour des applications d’alimentation DC/DC, grâce à la gestion de l’échauffement. Le courant de sortie des transformateurs piézoélectriques, et donc la puissance transmise, sont directement liés à la vitesse de vibration qui pour des valeurs élevées engendre des pertes et une forte élévation de température. Cette élévation excessive de la température a comme conséquence le changement des caractéristiques du transformateur et plus particulièrement la diminution du facteur de qualité Q. Ainsi cela entraine une limite structurelle de la puissance transmise du transformateur. Une solution pour augmenter le courant de sortie est l’utilisation d’un redresseur doubleur de courant, qui grâce à 2 inductances permet, à courant de charge donné, de diminuer la vitesse de vibration du transformateur, mais ne permet pas de régler le problème d’échauffement du transformateur. Dans cette thèse nous proposons des moyens d’évacuation de la chaleur ainsi que le choix de l’environnement dans lequel le transformateur devra fonctionner. L’influence de différents systèmes de refroidissement d’un convertisseur DC/DC à base transformateur piézoélectrique est étudiée. L’étude thermique du transformateur piézoélectrique multicouche polarisé en épaisseur et ayant des électrodes circulaires met en évidence un comportement non linéaire. Une plaque vibrante piézoélectrique est d’abord envisagée pour créer un flux d’air qui augmente l’évacuation de chaleur par convection, puis un module de refroidissement utilisant l’effet thermoélectrique. Les mesures montrent que la première solution est plus avantageuse car elle améliore sensiblement les performances du transformateur pour un coût énergétique très faible. Une étude thermique par éléments finis complète cette étude, montrant que l’approche par schéma électrique est pertinente. La puissance que peut délivrer le transformateur sur une charge optimale est encore augmentée. Enfin, ce travail montre qu’en combinant les dispositifs de refroidissement tout en respectant la condition de température inférieure à 55°C, le rendement du convertisseur reste raisonnable (70%) et la puissance disponible peut doubler dans le meilleur des cas. / The objective of this study was to increase the output current and power in a piezoelectric transformer (PT) based DC/DC converter by adding a cooling system. It is known that the output current of PT is limited by temperature build-up because of losses especially when driving at high vibration velocity. Excessive temperature rise will decrease the quality factor Q of piezoelectric component during the operational process. Simultaneously the vibration energy cannot be increased even if under higher excitation voltage. Although connecting different inductive circuits at the PT secondary terminal can increase the output current, the root cause of temperature build-up problem is not solved.This dissertation presents the heat transfer technology to deal with the temperature build-up problem. With the heat transfer technology, the threshold vibration velocity of PT can be increased and thus the output current and output power (almost three times).Furthermore, a comparison between heat transfer technology and current-doubler rectifier applied to the piezoelectric transformer based DC/DC converter was also studied. The advantages and disadvantages of the proposed technique were investigated. A theoretical-phenomenological model was developed to explain the relationship between the losses and the temperature rise. It will be shown that the vibration velocity as well as the heat generation increases the losses. In our design, the maximum output current capacity can increase 100% when the operating condition of PT temperature is kept below 55°C. The study comprises of a theoretical part and experimental proof-of-concept demonstration of the proposed design method.

Les téléphones et tablettes de dernière génération embarquent une puissance de calcul numérique très importante nécessitant une puissance électrique d’alimentation toute aussi significative. Afin de réduire la consommation énergétique des composants numériques complexes des terminaux mobiles, des techniques de modulation dynamique de la tension d’alimentation et de la fréquence de fonctionnement du cœur de calcul numérique sont utilisées. Le convertisseur DC/DC qui assure l’alimentation du cœur numérique doit donc faire face à de forts transitoires de charge, de tension de référence et de tension de source. Le contrôle en mode glissant d’un convertisseur DC/DC permet un bon compromis entre les performances transitoires du convertisseur, la réalisation via des composants analogiques et la puissance dissipée par le contrôleur. C’est pourquoi ce type de contrôle apparait être adapté au contrôle de convertisseurs DC/DC alimentant des cœurs numériques. Cette thèse a pour objet l’étude des alimentations sur carte électronique où le contrôleur et l’étage de puissance sont intégrés sur puce tandis que les composants de puissance passifs sont montés sur le circuit imprimé. Le contrôle en mode glissant à fréquence de découpage fixe d’un convertisseur DC/DC a été démontré avec des résultats significatifs. Cependant les performances transitoires d’un tel convertisseur sont amoindries en raison des délais introduits par une fréquence de découpage fixe. Une nouvelle structure de régulation de fréquence de découpage d’un convertisseur DC/DC contrôlé en mode glissant est proposée dans cette thèse. Cette structure régule la fréquence de découpage moyenne du convertisseur tout en maintenant la réponse transitoire du convertisseur asynchrone par rapport à l’horloge de référence. Une analyse de stabilité qui prend en compte les spécificités d’un tel système est aussi proposée. Le convertisseur a été conçu sur un procédé CMOS 130nm de STMicroelectronics. La fréquence de découpage est maintenue volontairement faible pour conserver un rendement élevé avec des composants passifs externes. Le prototype présente un rendement supérieur à 80% entre 2.4mW et 960mW de puissance de sortie. / Mobile applications necessitate nowadays huge digital-resources. Power management of a digital System-On-Chip (SOC) is based on dynamic voltage scaling. DC/DC converters used to supply the digital SoCs are facing stringent constraints with respect to load-transients, line-transients and reference tracking. Hysteretic control is known as the most convenient control scheme with a fair trade-off between transient performances, analog implementation and power consumption, particularly for one-phase architecture. The thesis focuses on-board DC/DC with a significant constraint on footprint (i.e. on components count and values). Fixed switching-frequency hysteretic control has been experimented with significant results. Transient performances are reduced due to latency introduced in the switching frequency control. The present study focuses on the improvement of the concept as well as its implementation and the analysis of stability. A new analog implementation of the sliding-mode control is presented with switching-frequency control using a particular analog phase-locked-loop but preserve transient performances. The DC/DC converter is implemented in CMOS 130nm by STMicroelectronics. The switching frequency range has been voluntarily limited and excludes the possible integration of passive components for the sake of silicon access. A hybrid demonstrator is presented with efficiency higher than 80\% between 2.4 mW and 960 mW output power.

The objective of the research is to develop a cost-effective high-power bi-directional dc/dc converter with low total-device ratings, reduced system parasitic effects, and a wide input/output range. Additional objectives of the research are to develop a small-signal model and control methods, and to present performance characterizations. Device stresses in the proposed topology are controlled to maintain minimal levels by varying the duty ratio and phase-shift angle between the primary and the secondary bridges, which results in a low total-device rating, when compared to conventional bi-directional dc/dc topologies. In the proposed topology, soft switching, which reduces power loss, can be realized under specific operating conditions. When the condition that causes minimal device stress is satisfied, zero-voltage switching (ZVS) can be obtained. In the research, ZVS capability is explored for a wide range of voltage conditions as well as for the minimal device-stress condition. The performance characterization includes verifying the soft-switching regions and power-loss estimation. Another part of the thesis is the controller design of the converter. Small-signal models and feedback controllers are developed, and the controllers are experimentally validated. Because in the isolated high-frequency converters, transformer saturation is an important issue, a method to prevent transformer saturation is proposed and experimentally validated.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Document formatted into pages; contains xvi, 209 p.; also includes graphics. Includes bibliographical references (p. 202-209). Available online via OhioLINK's ETD Center

Submitted by Alex de Sá Martins null (lex.martins@hotmail.com) on 2017-12-16T23:31:27Z No. of bitstreams: 1 ANÁLISE E PROJETO DO CONVERSOR FONTE-Y PARA USO....pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) / Approved for entry into archive by Maria Marlene Zaniboni null (zaniboni@bauru.unesp.br) on 2017-12-18T12:51:16Z (GMT) No. of bitstreams: 1 martins_as_me_bauru.pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) / Made available in DSpace on 2017-12-18T12:51:16Z (GMT). No. of bitstreams: 1 martins_as_me_bauru.pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) Previous issue date: 2017-10-26 / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Este trabalho aborda o estudo de topologia de conversor de energia baseada no uso de configuração de rede de impedância denominada fonte-Y, com o objetivo de ser aplicado em sistemas de geração distribuída de energia, em redes de baixa tensão. Em sistemas de geração distribuída de energia usualmente se faz necessária a existência de um estágio elevador de tensão e um estágio inversor, ambos controlados para produzir tensão e/ou corrente senoidal com mesma frequência, amplitude e fase da rede elétrica. Nesse sentido, este trabalho propõe a aplicação do conversor fonte- Y entre a geração e a conexão com e rede elétrica, de forma que as ações de conversão relacionadas com a elevação (CC-CC) e inversão (CC-CA) sejam efetuadas de forma integrada por uma única estrutura, contribuindo com a possibilidade de melhoria no rendimento global devido à minimização de estágios de conversão em cascata. Inicialmente, é efetuado um levantamento bibliográfico relacionando as principais topologias de conversores utilizando redes de impedância com indutores acoplados, considerando os aspectos operacionais, arranjo de impedância e ganho estático idealizado, desprezando perdas entre tensão de entrada e tensão máxima de saída obtida. Segue-se o estudo da operação de conversor CCCC empregando rede de impedância do tipo Y, definição das equações que regem o comportamento no tempo das tensões e correntes nos capacitores e indutores. É feita uma avaliação comparativa do ganho estático de tensão obtido e dos esforços nos semicondutores em função das variáveis de controle de projeto e operação disponíveis. Prossegue-se com o estudo da operação do conversor CC-CA empregando rede de impedância do tipo Y, considerando extensão das expressões encontradas para a operação como conversor CC-CC. Por fim, simulações computacionais foram desenvolvidas no ambiente PSIM contemplando o emprego dos circuitos e estratégias de modulação relacionadas com aplicações do conversor fonte- Y, em operação CC-CC e operação CC-CA visando a integração em sistemas de geração de energia, para demonstrar as vantagens e desvantagens do uso dessa topologia. / This paper deals with the study of energy converter topology based on the use of impedance network configuration called Y-source, with the objective of being applied in photovoltaic energy cogeneration systems in low voltage grids. In photovoltaic energy generation systems, it is usually necessary to have a voltage boost stage and an inverter stage, both controlled to produce voltage and / or sine current with the same frequency, amplitude and phase of the power grid. In this sense, this work proposes the application of the Y-source converter between the photovoltaic generation and the connection with the electric grid, so that the conversion actions related to elevation (DC-DC) and inversion (DC-AC) in a way integrated by a single structure, contributing to the possibility of improvement in the overall yield due to the minimization of cascade conversion stages. Initially a bibliographical survey was performed relating the main inverter topologies using impedance networks with coupled inductors considering the operational aspects, impedance arrangement and ideal static gain between the input voltage and the maximum output obtained. ext, the study of the DC-DC converter operation using the Y-type impedance network, definition of the equations governing the time behavior of the voltages and currents in the capacitors and inductors, is presented. It is also done the comparative evaluation of the static voltage gain obtained and the stresses in the semiconductors according to the available control and design control variables. Study of the operation of the DC-AC converter employing type Y impedance network, considering the extension of the expressions found for the operation as DC-DC converter. Finally, computational simulations were developed in the PSIM environment, considering the use of circuits and modulation strategies related to Y-source converter applications, in DC-DC operation and DC-AC operation for integration into power cogeneration systems, to demonstrate advantages and disadvantages of using this topology. / 134173/2017-1

DC to DC converters stabilize the voltage obtained from voltage sources such as solar power system, wind energy sources, wave energy sources, rectified voltage from alternators, and so forth. Hence, the need for improving its control algorithm is inevitable. Many algorithms are applied to DC to DC converters. This thesis designs fuzzy adaptive dynamic programming (Fuzzy ADP) algorithm. Also, this thesis implements both adaptive dynamic programming (ADP) and Fuzzy ADP on DC to DC converters to observe the performance of the output voltage trajectories.

Indiana University-Purdue University Indianapolis (IUPUI) / This research introduces a new design of a converter modified from SEPIC converter (Single end primary inductive converter), capable of generating desired voltage levels and polarities. The new switching converter topology allows for boost and buck of the input voltage theoretically achieving infinite positive and negative voltage levels. The proposed topology utilizes single high frequency switch to perform the power conversion which simplifies the design of the gate driver, but meanwhile, it still retains the ability to provide a wide range of output voltage. Mathematical modeling of the converter and computer simulations are validated by experimental data. To verify its performance a prototype was designed and built. It is experimentally proven that the circuit can generate a desired voltage in the range of voltages up to ±170 V, delivering 480 Watts of power to a resistive load.

No description available.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales. / The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.