Submitted by Alex de Sá Martins null (lex.martins@hotmail.com) on 2017-12-16T23:31:27Z No. of bitstreams: 1 ANÁLISE E PROJETO DO CONVERSOR FONTE-Y PARA USO....pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) / Approved for entry into archive by Maria Marlene Zaniboni null (zaniboni@bauru.unesp.br) on 2017-12-18T12:51:16Z (GMT) No. of bitstreams: 1 martins_as_me_bauru.pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) / Made available in DSpace on 2017-12-18T12:51:16Z (GMT). No. of bitstreams: 1 martins_as_me_bauru.pdf: 2723184 bytes, checksum: 9e77f24832992941e605e87a84c25d1a (MD5) Previous issue date: 2017-10-26 / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Este trabalho aborda o estudo de topologia de conversor de energia baseada no uso de configuração de rede de impedância denominada fonte-Y, com o objetivo de ser aplicado em sistemas de geração distribuída de energia, em redes de baixa tensão. Em sistemas de geração distribuída de energia usualmente se faz necessária a existência de um estágio elevador de tensão e um estágio inversor, ambos controlados para produzir tensão e/ou corrente senoidal com mesma frequência, amplitude e fase da rede elétrica. Nesse sentido, este trabalho propõe a aplicação do conversor fonte- Y entre a geração e a conexão com e rede elétrica, de forma que as ações de conversão relacionadas com a elevação (CC-CC) e inversão (CC-CA) sejam efetuadas de forma integrada por uma única estrutura, contribuindo com a possibilidade de melhoria no rendimento global devido à minimização de estágios de conversão em cascata. Inicialmente, é efetuado um levantamento bibliográfico relacionando as principais topologias de conversores utilizando redes de impedância com indutores acoplados, considerando os aspectos operacionais, arranjo de impedância e ganho estático idealizado, desprezando perdas entre tensão de entrada e tensão máxima de saída obtida. Segue-se o estudo da operação de conversor CCCC empregando rede de impedância do tipo Y, definição das equações que regem o comportamento no tempo das tensões e correntes nos capacitores e indutores. É feita uma avaliação comparativa do ganho estático de tensão obtido e dos esforços nos semicondutores em função das variáveis de controle de projeto e operação disponíveis. Prossegue-se com o estudo da operação do conversor CC-CA empregando rede de impedância do tipo Y, considerando extensão das expressões encontradas para a operação como conversor CC-CC. Por fim, simulações computacionais foram desenvolvidas no ambiente PSIM contemplando o emprego dos circuitos e estratégias de modulação relacionadas com aplicações do conversor fonte- Y, em operação CC-CC e operação CC-CA visando a integração em sistemas de geração de energia, para demonstrar as vantagens e desvantagens do uso dessa topologia. / This paper deals with the study of energy converter topology based on the use of impedance network configuration called Y-source, with the objective of being applied in photovoltaic energy cogeneration systems in low voltage grids. In photovoltaic energy generation systems, it is usually necessary to have a voltage boost stage and an inverter stage, both controlled to produce voltage and / or sine current with the same frequency, amplitude and phase of the power grid. In this sense, this work proposes the application of the Y-source converter between the photovoltaic generation and the connection with the electric grid, so that the conversion actions related to elevation (DC-DC) and inversion (DC-AC) in a way integrated by a single structure, contributing to the possibility of improvement in the overall yield due to the minimization of cascade conversion stages. Initially a bibliographical survey was performed relating the main inverter topologies using impedance networks with coupled inductors considering the operational aspects, impedance arrangement and ideal static gain between the input voltage and the maximum output obtained. ext, the study of the DC-DC converter operation using the Y-type impedance network, definition of the equations governing the time behavior of the voltages and currents in the capacitors and inductors, is presented. It is also done the comparative evaluation of the static voltage gain obtained and the stresses in the semiconductors according to the available control and design control variables. Study of the operation of the DC-AC converter employing type Y impedance network, considering the extension of the expressions found for the operation as DC-DC converter. Finally, computational simulations were developed in the PSIM environment, considering the use of circuits and modulation strategies related to Y-source converter applications, in DC-DC operation and DC-AC operation for integration into power cogeneration systems, to demonstrate advantages and disadvantages of using this topology. / 134173/2017-1

DC to DC converters stabilize the voltage obtained from voltage sources such as solar power system, wind energy sources, wave energy sources, rectified voltage from alternators, and so forth. Hence, the need for improving its control algorithm is inevitable. Many algorithms are applied to DC to DC converters. This thesis designs fuzzy adaptive dynamic programming (Fuzzy ADP) algorithm. Also, this thesis implements both adaptive dynamic programming (ADP) and Fuzzy ADP on DC to DC converters to observe the performance of the output voltage trajectories.

Indiana University-Purdue University Indianapolis (IUPUI) / This research introduces a new design of a converter modified from SEPIC converter (Single end primary inductive converter), capable of generating desired voltage levels and polarities. The new switching converter topology allows for boost and buck of the input voltage theoretically achieving infinite positive and negative voltage levels. The proposed topology utilizes single high frequency switch to perform the power conversion which simplifies the design of the gate driver, but meanwhile, it still retains the ability to provide a wide range of output voltage. Mathematical modeling of the converter and computer simulations are validated by experimental data. To verify its performance a prototype was designed and built. It is experimentally proven that the circuit can generate a desired voltage in the range of voltages up to ±170 V, delivering 480 Watts of power to a resistive load.

No description available.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales. / The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

No description available.

L'objectif de la thèse est de concevoir des compensateurs discrets qui permettent de compenser les non-linéarités introduites par les différents éléments dans la boucle de commande numérique, tout en maintenant des performances dynamiques élevées, des temps de développement rapide, et une structure reconfigurable. Ces compensateurs discrets doivent également avoir des temps de réponse rapide, avoir une déviation de la tension minimale et avoir, pour un étage de puissance donné, un temps de récupération rapide de la tension. Ces performances peuvent être atteintes par des compensateurs discrets conçus sur la base de techniques de contrôle linéaires et non linéaires. Pour obtenir une réponse rapide et stable, la thèse propose deux solutions : La première consiste à utiliser des techniques de contrôle linéaires et de concevoir le compensateur discret tout en gardant la bande passante la plus élevée possible. Il est communément admis que plus la bande passante est élevée, plus la réponse transitoire est rapide. L‘obtention d’une bande passante élevée, en utilisant des techniques de contrôle linéaires, est parfois difficile. Toutes ces situations sont mises en évidence dans la thèse. La seconde consiste à combiner les techniques de contrôle linéaires avec les techniques de contrôles non linéaires tels que la logique floue ou les réseaux de neurones. Les résultats de simulations ont permis de vérifier que la combinaison des contrôleurs non-linéaires avec les linéaires ont un meilleur rendement dynamique que les contrôleurs linéaires lorsque le point de fonctionnement varie. Avec l'aide des deux méthodes décrites ci-dessus, la thèse étudie également la technique de l’annulation des pôles-zéros (PZC) qui annule la fonction de transfert du convertisseur. Quelques modifications des techniques classiques de contrôle sont également proposées à partir de contrôleurs numériques afin d’améliorer les performances dynamiques. La thèse met également en évidence les non-linéarités qui dégradent les performances, propose les solutions permettant d'obtenir les meilleures performances, et lève les mystères du contrôle numérique. Une interface graphique est également introduite et illustrée dans le cas de la conception d'un convertisseur abaisseur de tension synchrone. En résumé, cette thèse décrit principalement l'analyse, la conception, la simulation, l’optimisation la mise en œuvre et la rentabilité des contrôleurs numériques. Une attention particulière est portée à l'analyse et l'optimisation des performances dynamique à haute fréquence et pour de faibles puissances des convertisseurs DC-DC abaisseur de tension. Ces convertisseurs fonctionnent en mode de conduction continue (CCM) à une fréquence de commutation de 1 MHz et s’appuie sur des techniques de contrôle linéaires et non linéaires de façon séquentielle. / The objective of the thesis is to design the discrete compensators which counteract the nonlinearities introduced by various elements in the digital control loop while delivering high dynamic performance, fast time-to-market and scalability. Excellent line and fast load transient response, which is a measure of the system response speed, with minimal achievable voltage deviation and a fast voltage recovery time for a given power stage can be achieved through the discrete compensators designed on the basis of linear and nonlinear control techniques. To achieve a stable and fast response, the thesis proposes two ways. One way is to use linear control techniques to design the discrete compensator while keeping the bandwidth higher. It is well-known fact that the higher the bandwidth, the faster is the transient response. Achieving higher bandwidth through linear control techniques sometimes becomes tricky. All those situations are highlighted in the thesis. The other way is to hybridize the linear control techniques with the nonlinear control techniques such as fuzzy logic or neural network based control techniques. Simulation results verify that hybridization of nonlinear controllers with the linear ones have better dynamic performance over linear controllers under the change of operating points. Along with using the two methodologies described above, the thesis also investigates the pole-zero cancellation (PZC) technique in which the poles and zeros of the compensator are placed in such a way that they cancel the effect of the poles or zeros of the buck converter to boost the phase margin at the required bandwidth. Some modifications are also suggested to the classical control techniques based digital controllers to improve the dynamic performance. The thesis highlights the nonlinearities which degrade the performance, a cost-effective solution that achieves good performance and the mysteries of digital control system. A graphical user interface is introduced and demonstrated for use with the design of a synchronous-buck converter. In summary, this thesis mainly describes the analysis, design, simulation, optimization, implementation and cost effectiveness of digital controllers with particular focus on the analysis and the optimization of the dynamic performance for high-frequency low-power DC-DC buck converter working in continuous conduction mode (CCM) operating at a switching frequency of 1 MHz using linear and nonlinear control techniques in a very sequential and comprehensive way.

Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on eliminating the issues associated with the state of the art switching converters by proposing three novel control techniques: (1) a digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range and provides seamless transition from buck to buck-boost modes (2) a hysteretic buck converter that employs a highly digital hybrid voltage/current mode control to regulate output voltage and switching frequency independently (3) a 10MHz continuous time PID controller using time based signal processing which alleviates the speed limitations associated with conventional analog and digital. All the three techniques employ digitally assisted control techniques and require no external compensation thus making the controllers fully integrated and highly cost effective. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from June 25, 2012 - June 25, 2014

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters