Les métaux nobles (Au, Ag, Pt, Ir, Pd et Ru) sont utilisés en salle blanche pour la réalisation de dispositifs électroniques ou peuvent être apportés par les équipements de fabrication (composants d’alliage par exemple). Il a été montré qu’ils pouvaient impacter fortement les dispositifs. Il est alors nécessaire de procéder au contrôle des équipements pour diagnostiquer au plus tôt une contamination. Or, il n’existe pas de technique industrielle pour leur suivi et ce à des niveaux d’au moins 5.109 at.cm-2 - recommandation ITRS. Il se pose la question de la pertinence de ces recommandations en fonction des types de dispositifs (SPAD notamment). Dans un premier temps, les travaux ont consisté à développer une technique physico-chimique pour l’analyse des métaux nobles sur silicium par VPD-DC-ICPMS. Enfin, leur dangerosité vis-à-vis des équipements et des dispositifs a été évaluée d’après leur comportement en température et le DCR généré sur SPAD. / Noble metals (Au, Ag, Pt, Ir, Pd and Ru) are used for the fabrication of microelectronics devices or can be brought by manufacturing tools (alloy components for example). It is well known that these impurities are detrimental to the efficiency of the devices. This implies a real and present need for control of their introduction in clean rooms to diagnose as soon as possible a contamination. Yet, there are no industrial technique for their follow-up at levels about 5.109 at.cm-2 - ITRS recommendations. The relevance of these recommendations according to the electronic device (SPAD in particular) could be questioned. At first, this study consisted in developing a physicochemical technique for the analysis of noble metals on Si wafers by VPD-DC-ICPMS. Then, their dangerousness towards tools and devices was established according to their behavior in temperature and the DCR generated on SPAD devices.

<p>Today the utilization of all kind of multimedia services in networks increases and due to this demand for real-time communication gets higher for every day. One of the most common protocols used today is Ethernet. It is of interest to find real-time protocols that are useful together with already existing protocols since it is expensive to rebuild the network infrastructure. Several new protocols have been proposed to solve the upcoming problems.</p><p>The objective of this project is to make an inventory and a comparison between Ethernet and these new protocols. During this project four different protocols capability to fulfill the demands for real-time communication have been studied and compared with Ethernet. Three of the protocols are built on the same basic technique as Ethernet and these are PCSMA, CSMA-DCR and DOD-CSMA-CD. The fourth protocol is ATM and it transmits in a different way over communication networks.</p><p>The analysis of this project is pointing out advantages, similarities and differences between the protocols from a real-time perspective. All four protocols are more suitable for real-time requirements than Ethernet.</p>

Today the utilization of all kind of multimedia services in networks increases and due to this demand for real-time communication gets higher for every day. One of the most common protocols used today is Ethernet. It is of interest to find real-time protocols that are useful together with already existing protocols since it is expensive to rebuild the network infrastructure. Several new protocols have been proposed to solve the upcoming problems. The objective of this project is to make an inventory and a comparison between Ethernet and these new protocols. During this project four different protocols capability to fulfill the demands for real-time communication have been studied and compared with Ethernet. Three of the protocols are built on the same basic technique as Ethernet and these are PCSMA, CSMA-DCR and DOD-CSMA-CD. The fourth protocol is ATM and it transmits in a different way over communication networks. The analysis of this project is pointing out advantages, similarities and differences between the protocols from a real-time perspective. All four protocols are more suitable for real-time requirements than Ethernet.

Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance. / Ph. D.

Bridge substructures are generally constructed using cast-in-place concrete and designed to undergo inelastic deformation in earthquake events. Although this construction approach has proven to be economical and provides adequate seismic performance through the formation of ductile plastic hinges, there are downsides relating to construction speed and quality, and post-earthquake repairability. This thesis explores two categories of Accelerated Bridge Construction (ABC) connection types, which use precast concrete instead of cast-in-place concrete to offer advantages including increased construction speed and quality. High Damage (HD) ABC connection types emulate the seismic behaviour of cast-in-place construction through the formation of ductile plastic hinges. Controlled Damage (CD) ABC connection types use unbonded post-tensioned precast connections to offer additional advantages including reduced residual drifts, limited and controlled damage and simple repair options. Novel buckling-restrained, fused mild steel energy dissipators suitable for use in CD connections are also developed and tested. These designs utilise 'dry' fabrication to simplify the fabrication process and minimise cost. Half-scale experimental testing is carried out to demonstrate both the assembly processes and behaviour under reversed cyclic uniaxial and biaxial loading representing an earthquake event. Following benchmark testing, repair strategies are applied to the CD connection types and the columns are tested again, representing a subsequent earthquake event. Good results are obtained from all cases with relatively straightforward construction and repair processes. With further developments and testing, the connection types proposed can provide competitive alternatives to conventional bridge pier design with regard to seismic performance and life cycle costs, with the additional benefits associated with precast construction.

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

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