Aircraft structural layout concept design at Saab Aeronautics utilize thickness optimizationto evaluate astructural layout concept. The thickness values can be used to compare conceptsto each other,and the bestonecan be further developed. Today, most ofthe creation and evaluation of structural layout concepts is manual work. Therefore, there is an ongoing investigation on how to implement design automation to reduce this manual and repetitive work. The investigationaims to achieve rapid exploration of the design space to find a good base for a new aircraft development. This includes investigating how the synchronization between a structural layout model (SLM) and a global finite element model (GFEM) can be improved. This thesis contributes to the investigation by exploring the possibilities to implement design automation in the creation of the SLM regarding the fuselage structure. Further, exploring the implementation of design automation in the creation of the GFEM to enable automatic evaluation of concepts. The thesis also explores how the synchronization between the models can be improved. To structure the thesis work, the software development methodologies of MOKA and RAD weremodified and combined. The execution of the thesis was carried out in the software of 3DEXPERIENCE, particularly using the applications CATIAand SIMULIA. This thesis work resulted in a methodfor developing and evaluating aircraft structure concept designs with design automation. The new method includes two models with corresponding scripts. The first model developed is a tool for a conceptualdesignerthat enables the creation of aircraft fuselage SLM from user defined inputs. The second model is generated by script which results in a GFEM with a direct connection to the SLM. To conclude, the developed method enables a faster iteration work of fuselage structural concept designs compared to the current method. The detail level is lower but more consistent and uniform. The GFEM was not able to fulfil its purpose in the developed method due to time limits and software limitations. However, the synchronization between the SLM and GFEM was implemented successfully and contained all critical elements.

The development of more complex products has increased dependency on virtual/digital models and emphasized the role of simulations as a means of validation before production. This level of dependency on digital models and simulation togetherwith the customization level and continuous requirement change leads to a large number of iterations in each stage of the product development process. This research, studies such group of products that have multidisciplinary, highly iterative, and simulation-driven design processes. It is shown that these high-level technical products, which are commonly outsourced to suppliers, commonly suffer from a long development lead time. The literature points to several research tracks including design automation and data-driven design with possible support. After studying the advantages and disadvantages of each track, a data-driven approachis chosen and studied through two case studies leading to two supporting tools that are expected to improve the development lead time in associated design processes. Feature extraction in CAD as a way to facilitate metamodeling is proposed as the first solution. This support uses the concept of the medial axis to find highly correlated features that can be used in regression models. As for the second supporting tool, an automated CAD script is used to produce a library of images associated with design variants. Dynamic relaxation is used to label each variant with its finite element solution output. Finally, the library is used to train a convolutions neural network that maps screenshots of CAD as input to finite element field answers as output. Both supporting tools can be used to create real-time prediction models in the early conceptual phases of the product development process to explore design space faster and reduce lead time and cost. / Utvecklingen av mer komplexa produkter har ökat beroendet av virtuella/digitala modeller och ökat betydelsen av simuleringar för att validera en produkt inför produktion. Ett stort beroende av digitala modeller och simulering tillsammans med den individuella anpassningen och kontinuerliga kravförändringar leder till ett stort antal iterationer i varje steg i produktutvecklingsprocessen. Forskningen som presenteras i denna avhandling studerar denna typ av produkter som har multidisciplinära, mycket iterativa och simuleringsdrivna designprocesser. Det har visat sig att dessa tekniska produkter på hög nivå, som vanligtvis tillhandahålls av underleverantörer, vanligtvis har en lång ledtid för utveckling. Litteraturstudien pekar på flera forskningsspår, exempelvis designautomation och datadriven design, eventuellt med stöd. Efter att ha studerat fördelarna och nackdelarna med varje spår, väljs det datadrivna tillvägagångssättet och studeras genom två fallstudier som leder till att två stödjande verktyg tas fram. De förväntas förbättra utvecklingsledtiden i tillhörande designprocesser. Feature extraktion i CAD som ett sätt att underlätta metamodellering föreslås som det första verktyget. Detta stöd använder medial axis för att hitta korrelerade features som kan användas i regressionsmodeller. När det gäller det andra stödjande verktyget används ett automatiserat CAD-skript för att producera ett stort bibliotek med bilder som är associerade olika designvarianter. Dynamisk relaxation används för att märka varje variant med dess finita elementlösning. Slutligen används detta bibliotek för att träna ett konvolutionerande neuralt nätverk som kartlägger skärmdumpar av CAD som indata till finita elementfältsvar som utdata. Båda stödverktygen kan användas för att skapa modeller för förutsägelser i realtid i de tidiga konceptuella faserna av produktutvecklingsprocessen för att utforska designrymden snabbare och minska ledtid och kostnader.

Integrated circuit development is an industry-driven high-risk high-stakes environment. The time from the concept of a new transistor technology to the market-ready product is measured in decades rather than months or years. This increases the risk for any company endeavouring on the journey of driving a new concept. Additionally to the return on investment being in the far future, it is only to be expected at all in high volume production, increasing the upfront investment. What makes the undertaking worthwhile are the exceptional gains that are to be expected, when the production reaches the market and enables better products. For these reasons, the adoption of new transistor technologies is usually based on small increments with foreseeable impact on the production process. Emerging semiconductor device development must be able to prove its value to its customers, the chip-producing industry, the earlier the better. With this thesis, I provide a new approach for early evaluation of emerging reconfigurable transistors in reconfigurable digital circuits. Reconfigurable transistors are a type of MOSFET that features a controllable conduction polarity, i.e., they can be configured by other input signals to work as PMOS or NMOS devices. Early device and circuit characterisation poses some challenges that are currently largely neglected by the development community. Firstly, to drive transistor development into the right direction, early feedback is necessary, which requires a method that can provide quantitative and qualitative results over a variety of circuit designs and must run mostly automatic. It should also require as little expert knowledge as possible to enable early experimentation on the device and new circuit designs together. Secondly, to actually run early, its device model should need as little data as possible to provide meaningful results. The proposed approach of this thesis tackles both challenges and employs model checking, a formal method, to provide a framework for the automated quantitative and qualitative analysis. It pairs a simple transistor device model with a charge transport model of the electrical network. In this thesis, I establish the notion of transistor-level reconfiguration and show the kinds of reconfigurable standard cell designs the device facilitates. Early investigation resulted in the discovery of certain modes of reconfiguration that the transistor features and their application to design reconfigurable standard cells. Experiments with device parameters and the design of improved combinational circuits that integrate new reconfigurable standard cells further highlight the need for a thorough investigation and quantification of the new devices and newly available standard cells. As their performance improvements are inconclusive when compared to established CMOS technology, a design space exploration of the possible reconfigurable standard cell variants and a context-aware quantitative analysis turns out to be required. I show that a charge transport model of the analogue transistor circuit provides the necessary abstraction, precision and compatibility with an automated analysis. Formalised in a DSL, it enables designers to freely characterise and combine parametrised transistor models, circuit descriptions that are device independent, and re-usable experiment setups that enable the analysis of large families of circuit variants. The language is paired with a design space exploration algorithm that explores all implementation variants of a Boolean function that employs various degrees and modes of reconfiguration. The precision of the device models and circuit performance calculations is validated against state-of-the-art FEM and SPICE simulations of production transistors. Lastly, I show that the exploration and analysis can be done efficiently using two important Boolean functions. The analysis ranges from worst-case measures, like delay, power dissipation and energy consumption to the detection and quantification of output hazards and the verification of the functionality of a circuit implementation. It ends in presenting average performance results that depend on the statistical characterisation of application scenarios. This makes the approach particularly interesting for measures like energy consumption, where average results are more interesting, and for asynchronous circuit designs which highly depend on average delay performance. I perform the quantitative analysis under various input and output load conditions in over 900 fully automated experiments. It shows that the complexity of the results warrants an extension to electronic design automation flows to fully exploit the capabilities of reconfigurable standard cells. The high degree of automation enables a researcher to use as little as a Boolean function of interest, a transistor model and a set of experiment conditions and queries to perform a wide range quantitative analyses and acquire early results.:1 Introduction 1.1 Emerging Reconfigurable Transistor Technology 1.2 Testing and Standard Cell Characterisation 1.3 Research Questions 1.4 Design Space Exploration and Quantitative Analysis 1.5 Contribution 2 Fundamental Reconfigurable Circuits 2.1 Reconfiguration Redefined 2.1.1 Common Understanding of Reconfiguration 2.1.2 Reconfiguration is Computation 2.2 Reconfigurable Transistor 2.2.1 Device geometry 2.2.2 Electrical properties 2.3 Fundamental Circuits 3 Combinational Circuits and Higher-Order Functions 3.1 Programmable Logic Cells 3.1.1 Critical Path Delay Estimation using Logical Effort Method 3.1.2 Multi-Functional Circuits 3.2 Improved Conditional Carry Adder 4 Constructive DSE for Standard Cells Using MC 4.1 Principle Operation of Model Checking 4.1.1 Model Types 4.1.2 Query Types 4.2 Overview and Workflow 4.2.1 Experiment setup 4.2.2 Quantitative Analysis and Results 4.3 Transistor Circuit Model 4.3.1 Direct Logic Network Model 4.3.2 Charge Transport Network Model 4.3.3 Transistor Model 4.3.4 Queries for Quantitative Analysis 4.4 Circuit Variant Generation 4.4.1 Function Expansion 5 Quantitative Analysis of Standard Cells 5.1 Analysis of 3-Input Minority Logic Gate 5.1.1 Circuit Variants 5.1.2 Worst-Case Analysis 5.2 Analysis of 3-Input Exclusive OR Gate 5.2.1 Worst-Case Analysis 5.2.2 Functional Verification 5.2.3 Probabilistic Analysis 6 Conclusion and Future Work 6.1 Future Work A Notational conventions B prism-gen Programming Interfaces Bibliography Terms & Abbreviations

Programming industrial robots for welding or part manipulation tasks is a time-consuming and complicated process, resulting in companies not able to implement robot systems and exploit their advantages. To reduce the time needed for programming, research is looking into ways to automate this process and reduce manual labour.In this thesis a concept for automating the programming process of industrial robots was investigated using EXCEL VBA and CATIA/DELMIA. It was done for an industrial grating model of varying sizes and configurations, resulting in a time reduction of 99% compared to manual creation. For this, the model was first automatically created from scratch for the required configuration and afterwards a robot motion was created fully automatically. The concept and modelling approach is described, and the automation approach detailed. Finally, the results are analysed and discussed.

The field of design automation aims to automate repetitive tasks in a workflow in order to free up time for more productive work. In this thesis, design automation with the help of AI techniques is investigated to streamline the pre-production work of expanded metal facades.  Two different problems concerning pre-production work are investigated in this thesis. The first one focuses on how to translate architectural drawings in pdf format to a bill of material. The second problem aims to develop a non-linear method for calculating the free area of the expanded metal facades. The method used for this project is an adaptation of the product development process with the inspiration of knowledge-based engineering.  For the first project, the AI method template matching was successfully used. With a script using this method, most of the panels are identified, except for panels where the drawings do not provide clear lines or where lines around the panels do not exist. The line quality in the architectural drawings was shown to impact the size estimation of the panels. In the second project, a non-linear machine learning model was developed. However, it was not managed within this project to get a good enough accuracy. The main reason for this is that it is suspected that the data is not accurate enough, nor are the 78 data points enough to train the model.

The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how hardware is compiled for achieving high performance, which requires a long computation time. How to efficiently compile a design becomes the bottleneck for FPGA reconfiguration. It is promising to apply some techniques or concepts from software to facilitate FPGA reconfiguration. This dissertation explores such an idea by utilizing three types of low-level manipulation on FPGA logic and routing resources, i.e. relocating, mapping/placing, and routing. It implements an FMA technique for "fast reconfiguration". The FMA makes use of the software compilation technique of reusing pre-compiled libraries for explicitly reducing FPGA compilation time. Based the software concept of Autonomic Computing, this dissertation proposes to build an Autonomous Adaptive System (AAS) to achieve "self-reconfiguration". An AAS absorbs the computing complexity into itself and compiles the desired change on its own. For routing, an FPGA router is developed. This router is able to route the MCNC benchmark circuits on five Xilinx devices within 0.35 ~ 49.05 seconds. Creating a routing-free sandbox with this router is 1.6 times faster than with OpenPR. The FMA uses relocating to load pre-compiled modules and uses routing to stitch the modules. It is an essential component of TFlow, which achieves 8 ~ 39 times speedup as compared to the traditional ISE flow on various test cases. The core part of an AAS is a lightweight embedded version of utilities for managing the system's hardware functionality. Two major utilities are mapping/placing and routing. This dissertation builds a proof-of-concept AAS with a universal UART transmitter. The system autonomously instantiates the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver. / Ph. D.

No description available.

O objetivo desta dissertação é propor o projeto de amplificadores de baixo rudo (LNAs) do tipo banda estreita e banda larga em tecnologia CMOS. O projeto de LNAs de banda estreita é representado através de um método de otimização conhecido como programação geométrica. Também, neste trabalho foi projetada uma topologia para LNAs de banda larga, aplicando a programação geométrica durante a fase inicial de projeto. Os layouts de ambos os circuitos foram desenhados e fabricados usando três processos CMOS diferentes. O aumento da utilização de circuitos digitais está reduzindo e substituindo a quantidade de circuitos analógicos implementados nos sistemas atuais. Nos transceptores de radiofrequência, a maior parte dos circuitos foi substituída por circuitos digitais equivalentes. A razão para esta substituição é devido a sua escalabilidade, variações PVT (Process, Voltage and Temperature) baixas, e menor tempo de projeto, resultado de um fluxo altamente automatizado. A redução do tempo de projeto representa um time-to-market menor e custos mais baixos. No entanto, o amplificador de baixo rudo é um dos blocos de radiofrequência que permanecem principalmente no domínio analógico, tornando a redução do tempo de projeto mediante a otimização do fluxo analógico como um bom foco de estudo. O LNA deve ser capaz de receber um sinal de baixa potência e alta frequência, e amplificá-lo adicionando o menor rudo possível, mantendo o casamento de impedâncias, baixo consumo de potência, e uma linearidade adequada a fim de evitar a distorção. Nesta dissertação, a maioria das especificações de desempenho citadas são formuladas rigorosamente e descritas como um programa geométrico. Além disso, vários scripts são escritos de forma a automatizar o fluxo de projeto. A programação geométrica é considerada como uma boa opção porque se o problema de otimização tem solução, o resultado é o ponto de otimização global, e pode ser atingido rapidamente (na ordem de segundos). Para um LNA fonte comum de banda estreita, o problema de projeto é completamente formulado como um programa geométrico, e alguns parâmetros normalmente desprezados, como as não idealidades dos indutores CMOS e a capacitância portadreno do transistor MOS são considerados no projeto. O problema de otimização é resolvido em minutos e testado em cinco processos CMOS diferentes, e para diferentes frequências de operação entre 1,5 GHz e 5 GHz. Os resultados são comparados e validados através de simulações, e dois layouts de LNAs para 2,45 GHz foram desenhados, fabricados e testados usando dois processos de 0,18 mm diferentes. Neste trabalho, também foi formulado um LNA de banda larga com cancelamento de rudo, e um bloco LNA-Misturador de banda larga é projetado incluindo a programação geométrica no cálculo da impedância de entrada e o cancelamento de rudo. Os layouts de dois protótipos diferentes do bloco LNA-Misturador de banda larga, operando na faixa de frequência entre 1 GHz e 5 GHz, foram desenhados e fabricados usando um processo de 0,18 mm. / This dissertation proposes the design of CMOS narrowband and wideband low noise amplifiers. The design problem of narrowband LNAs is represented as an optimization problem known as geometric programming. Furthermore, a topology for wideband LNAs is designed including the geometric programming in an early stage of the design. Both type of circuits were layouted and fabricated using three different CMOS processes. The tendency to increase the number of applications for digital-intensive circuitry, is reducing and replacing the amount of analog circuits implemented on systems nowadays. In radiofrequency transceivers, most of the circuits have been replaced by a digital-intensive counterpart. Digital circuitry is preferred over the analog one due to its scalability, low PVT (Process, Voltage and Temperature) variations, and shorter designing time result of a highly automated flow. The reduction of the designing time represents a faster time-to-market and lower costs. However, the low noise amplifier is one of the radiofrequency blocks that remain mainly in the analog domain, thus reducing its designing time by optimizing an analog design flow become a good focus of study. The LNA should be capable of receiving a low power and high frequency signal and amplify it adding the minimum noise possible, while maintaining good impedance matching, low power consumption and an adequate linearity in order to avoid distortion. In this dissertation, most of the performance parameters aforementioned are formulated rigorously and described as a geometric program. Moreover, various scripts are written in order to automate the design flow. The geometric programming is considered a good option because if the optimization problem is feasible, the result is the global optimum and can be obtained in seconds. For a common source narrowband LNA, the design problem is fully formulated as a geometric program and some parameters commonly neglected, as the CMOS inductors non-idealities and the gate-drain capacitance of MOS transistor are considered. The optimization problem is solved in minutes and tested on five different CMOS processes at different operating frequencies between 1.5 GHz and 5 GHz. The results are compared and validated through simulations, and two layouts for 2.45 GHz LNAs are drawn, fabricated and tested using two different 0.18 mm processes. In addition, a noise canceling wideband LNA is formulated, and a wideband LNA-Mixer cell is designed by including the geometric programming to estimate the input impedance matching and assure the noise cancelation. The layouts of two different prototypes of the wideband LNA-Mixer cells for the 1 GHz-5 GHz frequency band are drawn and fabricated using a 0.18 mm process.

O objetivo desta dissertação é propor o projeto de amplificadores de baixo rudo (LNAs) do tipo banda estreita e banda larga em tecnologia CMOS. O projeto de LNAs de banda estreita é representado através de um método de otimização conhecido como programação geométrica. Também, neste trabalho foi projetada uma topologia para LNAs de banda larga, aplicando a programação geométrica durante a fase inicial de projeto. Os layouts de ambos os circuitos foram desenhados e fabricados usando três processos CMOS diferentes. O aumento da utilização de circuitos digitais está reduzindo e substituindo a quantidade de circuitos analógicos implementados nos sistemas atuais. Nos transceptores de radiofrequência, a maior parte dos circuitos foi substituída por circuitos digitais equivalentes. A razão para esta substituição é devido a sua escalabilidade, variações PVT (Process, Voltage and Temperature) baixas, e menor tempo de projeto, resultado de um fluxo altamente automatizado. A redução do tempo de projeto representa um time-to-market menor e custos mais baixos. No entanto, o amplificador de baixo rudo é um dos blocos de radiofrequência que permanecem principalmente no domínio analógico, tornando a redução do tempo de projeto mediante a otimização do fluxo analógico como um bom foco de estudo. O LNA deve ser capaz de receber um sinal de baixa potência e alta frequência, e amplificá-lo adicionando o menor rudo possível, mantendo o casamento de impedâncias, baixo consumo de potência, e uma linearidade adequada a fim de evitar a distorção. Nesta dissertação, a maioria das especificações de desempenho citadas são formuladas rigorosamente e descritas como um programa geométrico. Além disso, vários scripts são escritos de forma a automatizar o fluxo de projeto. A programação geométrica é considerada como uma boa opção porque se o problema de otimização tem solução, o resultado é o ponto de otimização global, e pode ser atingido rapidamente (na ordem de segundos). Para um LNA fonte comum de banda estreita, o problema de projeto é completamente formulado como um programa geométrico, e alguns parâmetros normalmente desprezados, como as não idealidades dos indutores CMOS e a capacitância portadreno do transistor MOS são considerados no projeto. O problema de otimização é resolvido em minutos e testado em cinco processos CMOS diferentes, e para diferentes frequências de operação entre 1,5 GHz e 5 GHz. Os resultados são comparados e validados através de simulações, e dois layouts de LNAs para 2,45 GHz foram desenhados, fabricados e testados usando dois processos de 0,18 mm diferentes. Neste trabalho, também foi formulado um LNA de banda larga com cancelamento de rudo, e um bloco LNA-Misturador de banda larga é projetado incluindo a programação geométrica no cálculo da impedância de entrada e o cancelamento de rudo. Os layouts de dois protótipos diferentes do bloco LNA-Misturador de banda larga, operando na faixa de frequência entre 1 GHz e 5 GHz, foram desenhados e fabricados usando um processo de 0,18 mm. / This dissertation proposes the design of CMOS narrowband and wideband low noise amplifiers. The design problem of narrowband LNAs is represented as an optimization problem known as geometric programming. Furthermore, a topology for wideband LNAs is designed including the geometric programming in an early stage of the design. Both type of circuits were layouted and fabricated using three different CMOS processes. The tendency to increase the number of applications for digital-intensive circuitry, is reducing and replacing the amount of analog circuits implemented on systems nowadays. In radiofrequency transceivers, most of the circuits have been replaced by a digital-intensive counterpart. Digital circuitry is preferred over the analog one due to its scalability, low PVT (Process, Voltage and Temperature) variations, and shorter designing time result of a highly automated flow. The reduction of the designing time represents a faster time-to-market and lower costs. However, the low noise amplifier is one of the radiofrequency blocks that remain mainly in the analog domain, thus reducing its designing time by optimizing an analog design flow become a good focus of study. The LNA should be capable of receiving a low power and high frequency signal and amplify it adding the minimum noise possible, while maintaining good impedance matching, low power consumption and an adequate linearity in order to avoid distortion. In this dissertation, most of the performance parameters aforementioned are formulated rigorously and described as a geometric program. Moreover, various scripts are written in order to automate the design flow. The geometric programming is considered a good option because if the optimization problem is feasible, the result is the global optimum and can be obtained in seconds. For a common source narrowband LNA, the design problem is fully formulated as a geometric program and some parameters commonly neglected, as the CMOS inductors non-idealities and the gate-drain capacitance of MOS transistor are considered. The optimization problem is solved in minutes and tested on five different CMOS processes at different operating frequencies between 1.5 GHz and 5 GHz. The results are compared and validated through simulations, and two layouts for 2.45 GHz LNAs are drawn, fabricated and tested using two different 0.18 mm processes. In addition, a noise canceling wideband LNA is formulated, and a wideband LNA-Mixer cell is designed by including the geometric programming to estimate the input impedance matching and assure the noise cancelation. The layouts of two different prototypes of the wideband LNA-Mixer cells for the 1 GHz-5 GHz frequency band are drawn and fabricated using a 0.18 mm process.

No description available.