Le travail présenté dans ce mémoire traite de l'étude d'oscillateurs et d'Oscillateurs Contrôlés en Tension (OCT) différentiels couplés appliqués à la commande d'un réseau d’antennes linéaire. Après avoir rappelé les concepts d'antennes réseaux et d'oscillateurs, une synthèse de la théorie élaborée par R. York et donnant les équations dynamiques modélisant deux oscillateurs de Van der Pol couplés par un circuit résonnant a été présentée. Après avoir montré la limitation de cette approche concernant la prédiction de l'amplitude des oscillateurs, une nouvelle formulation des équations non linéaires décrivant les états de synchronisation a été proposée. Néanmoins, compte tenu du caractère trigonométrique et fortement non linéaire de ces équations, une nouvelle écriture facilitant la résolution numérique a été proposée. Ceci a permis l'élaboration d'un outil de Conception Assistée par Ordinateur (CAO) fournissant une cartographie de la zone de synchronisation de deux oscillateurs de Van der Pol couplés. Celle-ci permet de déterminer rapidement les fréquences d'oscillation libres nécessaires à l'obtention du déphasage souhaité. Pour ce faire, une procédure de modélisation de deux oscillateurs et OCTs différentiels couplés, par deux oscillateurs de Van der Pol couplés par une résistance a été élaborée. Les résultats fournis par l'outil de CAO proposé ont ensuite été comparés avec les résultats de simulations de deux oscillateurs et OCTs différentiels couplés obtenus avec le logiciel ADS d'Agilent. Une très bonne concordance des résultats a alors été obtenue montrant ainsi l'utilité et la précision de l'outil présenté. / The work presented in this thesis deals with the study of coupled differential oscillators and Voltage Controlled Oscillators (VCO) used to control antenna arrays. After reminding the concept of antenna arrays and oscillators, an overview of R. York's theory giving the dynamics for two Van der Pol oscillators coupled through a resonant network was presented. Then, showing the limitation of this approach regarding the prediction of the oscillators' amplitudes, a new formulation of the nonlinear equations describing the oscillators' locked states was proposed. Nevertheless, due to the trigonometric and strongly non-linear aspect of these equations, mathematical manipulations were applied in order to obtain a new system easier to solve numerically. This has allowed to the elaboration of a Computer Aided Design (CAD) tool, which provides a cartography giving the frequency locking region of two coupled differential Van der Pol oscillators. This cartography can help the designer to rapidly find the free-running frequencies of the two outermost differential oscillators or VCOs of the array required to achieve the desired phase shift. To do so, a modeling procedure of two coupled differential oscillators and VCOs as two coupled differential Van der Pol oscillators, with a resistive coupling network was performed. Then, in order to validate the results provided by our CAD tool, we compared them to the simulation results of two coupled differential oscillators and VCOs obtained with Agilent’s ADS software. Good agreements between the simulations of the circuits, the models and the theoretical results from our CAD tool were found.

Cette thèse porte sur le monitorage des simulations de circuits en signaux mixtes. Dans le domaine de la vérification de matériel, l'utilisation de formalismes déclaratifs pour la specification, dans le cadre de la validation par simulation, s'est installée dans la pratique courante. Cependant, le manque de fonctionnalités visant à spécifier les comportements asynchrones, ou l'intégration insuffisante des résultats de la vérification, rend les language d'assertions et de mesures inopérants pour la vérification de comportements en signaux mixtes. Nous proposons des outils théoriques et pratiques pour la description et le monitorage de ces comportements, qui comportent des aspects à la fois discrets et continus. Pour cela, nous nous appuyons sur des travaux antérieurs portant sur les extensions temps-réel de la logique temporelle et des expressions régulières. Nous décrivons de nouveaux algorithmes pour calculer la distance entre une trace de simulation et une propriété en logique temporelle données. Une nouvelle procédure de diagnostic est conçue pour déboguer efficacement de telles traces. Le monitorage des comportements continus est ensuite étendu à d'autres formes d'assertions basées sur des expressions régulières. Ces expressions constituent la base de notre language de description de mesures, qui permet de définir conjointement la mesure et les intervals temporels sur lesquels cette mesure doit être prise. Nous montrons comment d'autres mesures, déjà mises en œuvre dans les simulateurs analogiques peuvent être importées dans les descriptions digitales. Ceci permet d'étendre vers le domaine en signaux mixtes les approches hiérarchiques utilisées en vérification de circuits digitaux. / This thesis is concerned with the monitoring of mixed-signal circuit simulations. In the field of hardware verification, the use of declarative property languages in combination with simulation is now standard practice. However the lack of features to specify asynchronous behaviors, or the insufficient integration of verification results, makes existing assertion and measurement languages unable to enforce mixed-signal requirements. We propose several theoretical and practical tools for the description and automatic monitoring of such behaviors, that feature both discrete and continuous aspects. For this we build on previous work on real-time extensions of temporal logic and regular expressions. We describe new algorithms to compute the distance from some simulation trace to temporal logic specifications, whose complexity is not higher than traditional monitoring. A novel diagnostic procedure is provided in order to efficiently debug such traces. The monitoring of continuous behaviors is then extended to other forms of assertions based on regular expressions. These expressions form the basis of our measurement language, that describes conjointly a measure and the patterns over which that measure should be taken. We show how other measurements implemented in analog circuits simulators can be ported to digital descriptions, this way extending structured verification approaches used for digital designs toward mixed-signal.

Engineering designers commonly make sequential information acquisition decisions such as selecting designs for performance evaluation, selecting information sources, deciding whom to communicate with in design teams, and deciding when to stop design exploration. There is significant literature on normative decision making for engineering design, however, there is a lack of descriptive modeling of how designers actually make information acquisition decisions. Such descriptive modeling is important for accurately modeling design decisions, identifying sources of inefficiencies, and improving the design process. To that end, the research objective of the dissertation is to understand how designers make sequential information acquisition decisions and identify models that provide the best description of a designer’s decisions strategies. For gaining this understanding, the research approach consists of a synthesis of descriptive theories from psychological and cognitive sciences, along with empirical evidence from behavioral experiments under different design situations. Statistical Bayesian inference is used to determine how well alternate descriptive decision models describe the experimental data. This approach quantifies a designer's decision strategies through posterior parameter estimation and Bayesian model comparison. <br><br>Two research studies, presented in this dissertation, focus on assessing the effects of monetary incentives, fixed budget, type of design space exploration, and the availability of system-wide information on information acquisition decisions. The first study presented in this dissertation investigates information acquisition by an individual designer when multiple information sources are available and the total budget is limited. The results suggest that the student subjects' decisions are better represented by the heuristic-based models than the expected utility(EU)-based models. <br>While the EU-based models result in better net payoff, the heuristic models used by the subjects generate better design performance. The results also indicate the potential for nudging designers' decisions towards maximizing the net payoff by setting the fixed budget at low values and providing monetary incentives proportional to the saved budget.<br><br>The second study investigates information acquisition through communication. The focus is on designers’ decisions about whom to communicate with, and how much to communicate when there is interdependence between subsystems being designed. This study analyzes team communication of NASA engineers at a mission design laboratory (MDL) as well as of engineering students designing a simplified automotive engine in an undergraduate classroom environment. The results indicate that the rate of interactions increases in response to the reduce in system-level design performance in both settings. Additionally, the following factors seem to positively influence communication decisions: the pairwise design interdependence, node-wise popularity (significant with NASA MDL engineers due to large team size), and pairwise reciprocity.<br><br>The dissertation work increases the knowledge about engineering design decision making in following aspects. First, individuals make information acquisition decisions using simple heuristics based on in-situ information such as available budget amount and present system performance.<br>The proposed multi-discipline approach proves helpful for describing heuristics analytically and inferring context-specific decision strategies using statistical Bayesian inference. This work has potential application in developing decision support tools for engineering design. Second, the comparison of communication patterns between student design teams and NASA MDL teams reveals that the engine experiment preserves some but not all of the communication patterns of interest. We find that the representativeness depends not on matching subjects, tasks, and context separately, but rather on the behavior that results from the interactions of these three dimensions. This work provides lessons for designing representative experiments in the future.

This thesis covers the process of automating the design of coolant nozzles used for cylindrical grinding. Coolant nozzles are used to supply coolant, an oil and water mixture used to cool the metal workpiece and lubricate the grinding wheel. In the automotive industry, grinding is used to reduce the surface roughness of the workpiece. However, a large amount of heat is generated, risking the heat treatment of the steel to be compromised, for this, coolant is supplied to minimize the heat caused by friction. A nozzle is used, aiming a jet to the zone that generates heat. Commonly used nozzles are adjustable, leading to variation in cooling performance if misaligned. The design of fixed nozzles is developed in this thesis to reduce variation and automatise the design for multiple applications. The automatically designed nozzles are fused deposition modeled and tested. The design automation tool is tested repeatedly and improved successively in the span of the thesis. This lead to a great extent of implementation of design automation. Which lead to a facilitation in reaching of the work zone and avoid obstacles. Also, the tool managed to create nozzle tubes for a multitude of machines. The tool is able to generate, aim, orient, and individually dimension multi-nozzle tubes. Design of Experiment methodology is implemented to find nozzle designs with improved velocity and flow rate and minimize the air mixture with the coolant. Several nozzle designs are tested and fitted into a surrogate model that is, in turn, optimized. The results of the tests led to a greater understanding of how the nozzle geometry restricts the flow rate when attempts of reaching higher velocities of the coolant jet are made. The surrogate models created, also made it possible to find the range of designs which best suits different applications, whereby a Pareto front was able to be populated with a range of different designs alternating in flow rate, velocity and coherency ratio.

Air intakes are complex components that are critical for the propulsion of the aircraft. The design has to consider requirements from several different departments, often contradictory. Additionally, the air intakes need to cooperate with other critical components. This makes testing of the models crucial, hence time-demanding. Design automation is a growing field which aims at minimizing repetitive work during product concept development. To follow the increasing digitalization, further investigations of design automation applied on air intakes are significant.  The application Imagine and Shape in 3D Experience CATIA handles subdivided surfaces. These surfaces are both flexible and provide a high order of continuity, which is often desired. While design automation in CATIA is well investigated, design automation in Imagine and Shape is not.  Knowledge based engineering techniques are often used to implement design automation. The methodology MOKA is frequently used when developing knowledge based engineering applications. This master thesis has followed MOKA in combination with Scrum.  The master thesis has resulted in a method to allow automation in Imagine and Shape by linking mesh nodes on subdivided surfaces to reference points that are parameterized. Further, a method for generating air intake configurations as well as the integration with a fuselage has been developed. The method includes wireframe models in Generative Shape Design, subdivided surfaces in Imagine and Shape, scripts in EKL as well as UserForm and scripts in VBA. Additionally, the order of continuity for an integration between air intakes and fuselage has been analyzed using tools in 3D Experience CATIA.  A conclusion drawn is that the method for generating air intakes cannot be completely automated. Instantiation and dimension of components can be automated, but manual work is required when using tools in Imagine and Shape during the integration between the components and the fuselage.Two methods for linking mesh nodes to reference points have been identified, one manual and one semi-automatic. The automatic method saves time and mouse clicks by utilizing VBA scripts. Further, the achieved order of continuity of an integration between subdivided surfaces depends on the individual components.

In the building automation domain, there are gaps among various tasks related to design engineering. As a result created system designs must be adapted to the given requirements on system functionality, which is related to increased costs and engineering effort than planned. For this reason standards are prepared to enable a coordination among these tasks by providing guidelines and unified artifacts for the design. Moreover, a huge variety of prefabricated devices offered from different manufacturers on the market for building automation that realize building automation functions by preprogrammed software components. Current methods for design creation do not consider this variety and design solution is limited to product lines of a few manufacturers and expertise of system integrators. Correspondingly, this results in design solutions of a limited quality. Thus, a great optimization potential of the quality of design solutions and coordination of tasks related to design engineering arises. For given design requirements, the existence of a high number of devices that realize required functions leads to a combinatorial explosion of design alternatives at different price and quality levels. Finding optimal design alternatives is a hard problem to which a new solution method is proposed based on heuristical approaches. By integrating problem specific knowledge into algorithms based on heuristics, a promisingly high optimization performance is achieved. Further, optimization algorithms are conceived to consider a set of flexibly defined quality criteria specified by users and achieve system design solutions of high quality. In order to realize this idea, optimization algorithms are proposed in this thesis based on goal-oriented operations that achieve a balanced convergence and exploration behavior for a search in the design space applied in different strategies. Further, a component model is proposed that enables a seamless integration of design engineering tasks according to the related standards and application of optimization algorithms.

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation. / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.

This dissertation describes the development, design, implementation and evaluation of a data acquisition system, with the main aim of using it for data collection on a laboratory pilot ball mill. An open-source prototype hardware platform was utilised in the implementation of the data acquisition function, however, with limitations. An analogue signal conditioning card has been successfully developed to interface the analogue signals to the dual domain ADC module. Model-based software development was used to design and develop the algorithms to control the DAS acquisition process, but with limited capabilities. A GUI application has been developed and used for the collection and storage of the raw data on the host system. The DAS prototype was calibrated and collected data successfully through all the channels; however, the input signal bandwidth was limited to 2Hz. / Electrical and Mining Engineering / M. Tech. (Electrical Engineering)

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography