Fundação de Amparo à Pesquisa do Estado do Rio de Janeiro / Neste trabalho discutimos vários sistemas de dígitos verificadores utilizados no Brasil, muitos deles semelhantes a esquemas usados mundialmente, e fazemos uma análise da sua capacidade de detectar os diversos tipos de erros que são comuns na entrada de dados em sistemas computacionais. A análise nos mostra que os esquemas escolhidos constituem decisões subotimizadas e quase nunca obtêm a melhor taxa de detecção de erros possível. Os sistemas de dígitos verificadores são baseados em três teorias da álgebra: aritmética modular, teoria de grupos e quasigrupos. Para os sistemas baseados em aritmética modular, apresentamos várias melhorias que podem ser introduzidas. Desenvolvemos um novo esquema ótimo baseado em aritmética modular base 10 com três permutações para identificadores de tamanho maior do que sete. Descrevemos também o esquema Verhoeff, já antigo, mas pouquíssimo utilizado e que também é uma alternativa de melhoria para identificadores de tamanho até sete. Desenvolvemos ainda, esquemas ótimos para qualquer base modular prima que detectam todos os tipos de erros considerados. A dissertação faz uso ainda de elementos da estatística, no estudo das probabilidades de detecção de erros e de algoritmos, na obtenção de esquemas ótimos. / In this paper we present several check digit systems used in Brazil, many of them similar to schemes used worldwide, and we do an analysis of their ability to detect various types of errors that are common in data entry computer systems. This analysis shows that the schemes constitute suboptimal decisions and almost never get the best rate possible error detection. Check digit schemes are based on three algebra theory: modular arithmetic, group theory and quasigroup. For the schemes based on modular arithmetic we present several improvements that can be made. We developed a new optimal scheme based on modular arithmetic base 10 with three permutations for identifers larger than 7. We also present the Verhoeff scheme, already old but used very little and that is also a good alternative for improvement identifers for size up to 7. We have also developed,optimum schemes for any modular base prime that detect all types of errors considered. The dissertation also makes use of elements of statistics in the study of the probability of error detection and algorithms to obtain optimal schemes.

Nos últimos anos, os sistemas integrados em silício (SOCs - Systems-on-Chip) têm se tornado menos imunes a ruído, em decorrência dos ajustes necessários na tecnologia CMOS (Complementary Metal-Oxide-Silicon) para garantir o funcionamento dos transistores com dimensões nanométricas. Dentre tais ajustes, a redução da tensão de alimentação e da tensão de limiar (threshold) tornam os SOCs mais suscetíveis a falhas transientes, principalmente aquelas provocadas pela colisão de partículas energéticas que provêm do espaço e encontram-se presentes na atmosfera terrestre. Quando uma partícula energética de alta energia colide com o dreno de um transistor que está desligado, ela perde energia e produz pares elétron-lacuna livres, resultando em uma trilha de ionização. A ionização pode gerar um pulso transiente de tensão que pode ser interpretado como uma mudança no sinal lógico. Em um circuito combinacional, o pulso pode propagar-se até ser armazenado em um elemento de memória. Tal fenômeno é denominado Single-Event Transient (SET). Como a tendência é que as dimensões dos dispositivos fabricados com tecnologia CMOS continuem reduzindo por mais alguns anos, a ocorrência de SETs em SOCs operando na superfície terrestre tende a aumentar, exigindo a adoção de técnicas de tolerância a falhas no projeto de SOCs. O presente trabalho tem por objetivo avaliar circuitos somadores tolerantes a falhas transientes encontrados na literatura. Duas arquiteturas de somadores foram escolhidas: Ripple Carry Adder (RCA) e Binary Signed Digit Adder (BSDA). O RCA foi escolhido por ser o tipo de somador de menor custo e por isso, amplamente utilizado em SOCs. Já o BSDA foi escolhido porque utiliza o sistema numérico de dígito binário com sinal (Binary Signed Digit – BSD). Por ser um sistema de representação redundante, o uso de BSD facilita a aplicação de técnicas de tolerância a falhas baseadas em redundância de informação. Os somadores protegidos avaliados foram projetados com as seguintes técnicas: Redundância Modular Tripla (Triple Modular Redundancy - TMR) e Recomputação com Entradas e Saídas Invertidas (RESI), no caso do RCA, e codificação 1 de 3 e verificação de paridade, no caso do BSDA. As 9 arquiteturas de somadores foram simuladas no nível elétrico usando o Modelo Tecnológico Preditivo (Predictive Technology Model - PTM) de 45nm e considerando quatro comprimentos de operandos: 4, 8, 16 e 32 bits. Os resultados obtidos permitiram quantificar o número de transistores, o atraso crítico e a potência média consumida por cada arquitetura protegida. Também foram realizadas campanhas de injeção de falhas, por meio de simulações no nível elétrico, para estimar o grau de proteção de cada arquitetura. Os resultados obtidos servem para guiar os projetistas de SOCs na escolha da arquitetura de somador tolerante a falhas mais adequada aos requisitos de cada projeto. / In the past recent years, integrated systems on a chip (Systems-on-chip - SOCs) became less immune to noise due to the adjusts in CMOS technology needed to assure the operation of nanometric transistors. Among such adjusts, the reductions in supply voltage and threshold voltage make SOSs more susceptible to transient faults, mainly those provoked by the collision of charged particles coming from the outer space that are present in the atmosphere. When a heavily energy charged particle hits the drain region of a transistor that is at the off state it produces free electron-hole pairs, resulting in an ionizing track. The ionization may generate a transient voltage pulse that can be interpreted as a change in the logic signal. In a combinational circuit, the pulse may propagate up to the primary outputs and may be captured by the output storage element. Such phenomenon is referred to as Single-Event Transient (SET). Since it is expected that transistor dimensions will continue to reduce in the next technological nodes, the occurrence of SETs at Earth surface will increase and therefore, fault tolerance techniques will become a must in the design of SOSs. The present work targets the evaluation of transient fault-tolerant adders found in the literature. Two adder architectures were chosen: the Ripple-Carry Adder (RCA) and the Binary Signed Digit Adder (BSDA). The RCA was chosen because it is the least expensive and therefore, the most used architecture for SOS design. The BSDA, in turn, was chosen because it uses the Binary Signed Digit (BSD) system. As a redundant number system, the BSD paves the way to the implementation of fault-tolerant adders using information redundancy. The evaluated fault-tolerant adders were implemented by using the following techniques: Triple Module Redundancy (TMR) and Recomputing with Inverted Inputs and Outputs (RESI), in the case of the RCA, and 1 out of 3 coding and parity verification, in the case of the BSDA. A total of 9 adder architectures were simulated at the electric-level using the Predictive Technology Model (PTM) for 45nm in four different bitwidths: 4, 8, 16 and 32. The obtained results allowed for quantifying the number of transistors, critical delay and average power consumption for each fault-tolerant architecture. Fault injection campaigns were also accomplished by means of electric-level simulations to estimate the degree of protection of each architecture. The results obtained in the present work may be used to guide SOS designers in the choice of the fault-tolerant adder architecture that is most likely to satisfy the design requirements.

Nos últimos anos, os sistemas integrados em silício (SOCs - Systems-on-Chip) têm se tornado menos imunes a ruído, em decorrência dos ajustes necessários na tecnologia CMOS (Complementary Metal-Oxide-Silicon) para garantir o funcionamento dos transistores com dimensões nanométricas. Dentre tais ajustes, a redução da tensão de alimentação e da tensão de limiar (threshold) tornam os SOCs mais suscetíveis a falhas transientes, principalmente aquelas provocadas pela colisão de partículas energéticas que provêm do espaço e encontram-se presentes na atmosfera terrestre. Quando uma partícula energética de alta energia colide com o dreno de um transistor que está desligado, ela perde energia e produz pares elétron-lacuna livres, resultando em uma trilha de ionização. A ionização pode gerar um pulso transiente de tensão que pode ser interpretado como uma mudança no sinal lógico. Em um circuito combinacional, o pulso pode propagar-se até ser armazenado em um elemento de memória. Tal fenômeno é denominado Single-Event Transient (SET). Como a tendência é que as dimensões dos dispositivos fabricados com tecnologia CMOS continuem reduzindo por mais alguns anos, a ocorrência de SETs em SOCs operando na superfície terrestre tende a aumentar, exigindo a adoção de técnicas de tolerância a falhas no projeto de SOCs. O presente trabalho tem por objetivo avaliar circuitos somadores tolerantes a falhas transientes encontrados na literatura. Duas arquiteturas de somadores foram escolhidas: Ripple Carry Adder (RCA) e Binary Signed Digit Adder (BSDA). O RCA foi escolhido por ser o tipo de somador de menor custo e por isso, amplamente utilizado em SOCs. Já o BSDA foi escolhido porque utiliza o sistema numérico de dígito binário com sinal (Binary Signed Digit – BSD). Por ser um sistema de representação redundante, o uso de BSD facilita a aplicação de técnicas de tolerância a falhas baseadas em redundância de informação. Os somadores protegidos avaliados foram projetados com as seguintes técnicas: Redundância Modular Tripla (Triple Modular Redundancy - TMR) e Recomputação com Entradas e Saídas Invertidas (RESI), no caso do RCA, e codificação 1 de 3 e verificação de paridade, no caso do BSDA. As 9 arquiteturas de somadores foram simuladas no nível elétrico usando o Modelo Tecnológico Preditivo (Predictive Technology Model - PTM) de 45nm e considerando quatro comprimentos de operandos: 4, 8, 16 e 32 bits. Os resultados obtidos permitiram quantificar o número de transistores, o atraso crítico e a potência média consumida por cada arquitetura protegida. Também foram realizadas campanhas de injeção de falhas, por meio de simulações no nível elétrico, para estimar o grau de proteção de cada arquitetura. Os resultados obtidos servem para guiar os projetistas de SOCs na escolha da arquitetura de somador tolerante a falhas mais adequada aos requisitos de cada projeto. / In the past recent years, integrated systems on a chip (Systems-on-chip - SOCs) became less immune to noise due to the adjusts in CMOS technology needed to assure the operation of nanometric transistors. Among such adjusts, the reductions in supply voltage and threshold voltage make SOSs more susceptible to transient faults, mainly those provoked by the collision of charged particles coming from the outer space that are present in the atmosphere. When a heavily energy charged particle hits the drain region of a transistor that is at the off state it produces free electron-hole pairs, resulting in an ionizing track. The ionization may generate a transient voltage pulse that can be interpreted as a change in the logic signal. In a combinational circuit, the pulse may propagate up to the primary outputs and may be captured by the output storage element. Such phenomenon is referred to as Single-Event Transient (SET). Since it is expected that transistor dimensions will continue to reduce in the next technological nodes, the occurrence of SETs at Earth surface will increase and therefore, fault tolerance techniques will become a must in the design of SOSs. The present work targets the evaluation of transient fault-tolerant adders found in the literature. Two adder architectures were chosen: the Ripple-Carry Adder (RCA) and the Binary Signed Digit Adder (BSDA). The RCA was chosen because it is the least expensive and therefore, the most used architecture for SOS design. The BSDA, in turn, was chosen because it uses the Binary Signed Digit (BSD) system. As a redundant number system, the BSD paves the way to the implementation of fault-tolerant adders using information redundancy. The evaluated fault-tolerant adders were implemented by using the following techniques: Triple Module Redundancy (TMR) and Recomputing with Inverted Inputs and Outputs (RESI), in the case of the RCA, and 1 out of 3 coding and parity verification, in the case of the BSDA. A total of 9 adder architectures were simulated at the electric-level using the Predictive Technology Model (PTM) for 45nm in four different bitwidths: 4, 8, 16 and 32. The obtained results allowed for quantifying the number of transistors, critical delay and average power consumption for each fault-tolerant architecture. Fault injection campaigns were also accomplished by means of electric-level simulations to estimate the degree of protection of each architecture. The results obtained in the present work may be used to guide SOS designers in the choice of the fault-tolerant adder architecture that is most likely to satisfy the design requirements.

In an initial experiment (Wilson and Weakley, 2004), word recognition was assessed with six digit triplets presented at 14 signal-to-babble ratios (S/B) in 2 dB steps. An abbreviated version of the protocol was developed for clinic use involving three digit triplets at 7 S/Bs in 4 dB steps. The purpose of this experiment was to examine the relationship between the two digit protocols with comparisons made with other variables including age, pure-tone thresholds, subjective measures of understanding speech in quiet and in noise, and word recognition of monosyllabic words in quiet and in babble. Ninety-six listeners with sensorineural hearing loss participated. For equivalent performance, the short version of the digit triplets required (1) a 2.6 dB more favorable S/B than the long version and (2) a 15.1 dB less favorable S/B than the words. Age, hearing loss, and subjective evaluation of the ability to understand speech in quiet and in noise were not related to performance on digits or words in multitalker babble.

Background: While farmers' markets are a potential strategy to increase access to fruits and vegetables in rural areas, more information is needed regarding use of farmers' markets among rural residents. Thus, this study's purpose was to examine (1) socio-demographic characteristics of participants; (2) barriers and facilitators to farmers' market shopping in southern rural communities; and (3) associations between farmers' market use with fruit and vegetable consumption and body mass index (BMI). Methods. Cross-sectional surveys were conducted with a purposive sample of farmers' market customers and a representative sample of primary household food shoppers in eastern North Carolina (NC) and the Appalachian region of Kentucky (KY). Customers were interviewed using an intercept survey instrument at farmers' markets. Representative samples of primary food shoppers were identified via random digit dial (RDD) cellular phone and landline methods in counties that had at least one farmers' market. All questionnaires assessed socio-demographic characteristics, food shopping patterns, barriers to and facilitators of farmers' market shopping, fruit and vegetable consumption and self-reported height and weight. The main outcome measures were fruit and vegetable consumption and BMI. Descriptive statistics were used to examine socio-demographic characteristics, food shopping patterns, and barriers and facilitators to farmers' market shopping. Linear regression analyses were used to examine associations between farmers' market use with fruit and vegetable consumption and BMI, controlling for age, race, education, and gender. Results: Among farmers' market customers, 44% and 55% (NC and KY customers, respectively) reported shopping at a farmers' market at least weekly, compared to 16% and 18% of NC and KY RDD respondents. Frequently reported barriers to farmers' market shopping were market days and hours, "only come when I need something", extreme weather, and market location. Among the KY farmers' market customers and NC and KY RDD respondents, fruit and vegetable consumption was positively associated with use of farmers' markets. There were no associations between use of farmers' markets and BMI. Conclusions: Fruit and vegetable consumption was associated with farmers' market shopping. Thus, farmers' markets may be a viable method to increase population-level produce consumption.

This thesis aims to implement a segmentation-free strategy in the context of handwritten multi-digit string recognition. Three models namely VGG-16, CRNN and 4C are built to be evaluated and benchmarked, also research about the effect of the different training set on model performance is carried out.

Support vector machines (SVMs) are a powerful tool for classification problems. SVMs have only been developed in the last 20 years with the availability of cheap and abundant computing power. SVMs are a non-statistical approach and make no assumptions about the distribution of the data. Here support vector machines are applied to a classic data set from the machine learning literature and the out-of-sample misclassification rates are compared to other classification methods. Finally, an algorithm for using support vector machines to address the difficulty in imputing missing categorical data is proposed and its performance is demonstrated under three different scenarios using data from the 1997 National Labor Survey.

According to the Americans with Disabilities Act, universities and colleges are required to provide accommodative services for students with disabilities. Many studies have examined the role of malingering mental health symptoms in order to obtain psychotropic medications, but very little research has been done on the role of accommodations as secondary gain in students who may malinger learning disabilities. This study sought to examine both the usefulness of implementing specific malingering detection measures in psychological evaluations with university students and the agreement of those measures within the population. Archival data was gathered from a university accommodation clinic that provided free psychological evaluations for consecutively presenting students (N=121). Four malingering detection measures were used: the Test of Memory and Malingering (TOMM), the Word Memory Test (WMT), the WAIS Digit Span (DS) and two cut scores for the MMPI-2 F Scale (F Scale 80 and F Scale 95). Scores for these four malingering detection measures were compared in terms of their agreement rates, their classification rates (at a 10% malingering base rate recommendation), and their sensitivity, specificity, positive and negative predictive powers using both the TOMM and WMT independently as diagnostic criterion. A qualitative examination of the data revealed that different combinations of measures did classify some of the same respondents as malingering. Results indicated that each of these four measures share the ability to detect malingering in its different forms and have similar classification rates. Although the TOMM and WMT likely provide overlapping information, the pragmatic implementation of one of these measures may assist in the evaluation of suspected malingering with accommodation-seeking students.

No description available.

Yes / Objective: This study investigated whether dual tasks make disproportionately high demands in Huntington’s disease (HD) compared with controls, and also tested the Multiple Resources Theory. Method: Thirteen HD participants and 13 controls completed 2 dual task sets that varied in difficulty and complexity: Set 1 paired simple choice reaction time (RT) with digit forward, and Set 2 paired complex choice RT with digit backward. Results: We found that HD participants were overall slower; however, although they maintained similar levels of accuracy in the simple choice RT tasks with controls, their accuracy decreased in the complex choice RT tasks. In addition, we found that HD participants were more susceptible to speed-accuracy trade-offs. Despite that, they did not show greater dual task costs than controls. Conclusions: Overall, our findings do not support the Multiple Resources Theory, but they do provide some support for the Unitary Resource Theory and the attentional impairment hypothesis.