Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

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Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-16T07:16:47Z (GMT). No. of bitstreams: 1 Lima_JoseErickdeSouza_M.pdf: 6787187 bytes, checksum: 105b3b5aec8638e48cd17d79b4962b1d (MD5) Previous issue date: 2010 / Resumo: Este trabalho descreve um sistema constituído de diversos instrumentos, que se encontram interligados e gerenciados por um aplicativo de software, implementando um ambiente compacto para a caracterização de conversores analógico-digitais, de acordo com os procedimentos descritos nas normas IEEE 1057-1994 e IEEE 1241-2000. O sistema desenvolvido possui limitações quanto aos tipos de conversores analógico-digitais que podem ser testados, devidas às restrições impostas pelos equipamentos disponíveis neste momento. Sua estrutura, no entanto, foi concebida para permitir a expansão destes limites com a troca dos instrumentos limitantes à medida que estes forem adquiridos. A avaliação da sua funcionalidade foi realizada testando dois conversores analógico-digitais que têm características distintas. Enquanto um dos dispositivos testados tem resolução nominal de 10 bits e taxa de conversão de 80 MSPS, o outro tem resolução de 8 bits e taxa de conversão nominal de 8kSPS. A motivação para o desenvolvimento deste sistema está no projeto de conversores analógico-digitais integrados que se encontra em andamento no LPM-FEEC-Unicamp. A disponibilidade de um ambiente de teste com as propriedades do sistema desenvolvido é um requisito importante para o sucesso do projeto, pois viabiliza a verificação imediata dos circuitos construídos, reduzindo o tempo de convergência às metas do projeto / Abstract: This paper describes a system composed of various instruments, which are interconnected and managed by a software application, implementing a compact environment for characterization of analog-digital converters, according to the procedures described in IEEE 1057-1994 and IEEE 1241 -2000. The developed system has limitations on the kinds of analog-digital converters that can be tested due to restrictions imposed by the equipment available at the moment. Its structure, however, was designed to allow the expansion of these limits with the exchange of the limiting instruments as they are acquired. The evaluation of its functionality was performed by testing two analog-digital converters that have distinct characteristics. While one of the tested devices has nominal resolution of 10 bits and conversion rate of 80 MSPS, the other has 8-bit resolution and conversion rate four orders of magnitude below. The motivation for developing this system is the design of integrated analog-digital converters that is being carried on at the LPM-FEEC-Unicamp. The availability of a test environment with the properties of the developed system is an important requisite for the success of the project because it enables the immediate verification of the constructed circuits, thus reducing the convergence time to the project goals / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-22T08:24:56Z (GMT). No. of bitstreams: 1 Abdnur_ThiagoBorges_M.pdf: 3580657 bytes, checksum: 2f83cda26eeb7b31a6ed647c31e27117 (MD5) Previous issue date: 2012 / Resumo: Com a mudança da maior parte das arquiteturas convencionais para multi-core a comunica _cão entre as diferentes unidades de processamento se torna um problema de destaque, principalmente no que tange _a transferência de dados entre cores. Apesar do enorme impacto no desempenho, é limitado o número de trabalhos científicos que tratam sobre novas soluções para o problema, o foco mais comum é realizar a comunicação através da memória ou endereços específicos mapeados em memória. Nesta dissertação foi definido um modelo de comunicação que acrescenta três novas instruções ao conjunto de instruções do SPARCv8, permitindo que diferentes cores transportem dados entre si diretamente, sem a latência derivada do uso de uma memória compartilhada e de Lucas, como _e o caso da atual implementação do LEON3. Avaliou-se esse modelo de comunicação através de diversos tipos de aplicações sintéticas como produtor-consumidor e pipeline. Para tornar o protótipo em FPGA mais realista, também foi construído um modelo de atraso para a memória principal do sistema, para que o desempenho relativo entre processador e memória _que mais próximo do real. Foi adicionado um suporte básico _as novas instruções no compilador para seu uso em código C através de asm-inline. De forma geral, obteve-se ganhos de 3% _a até 70 vezes, em termos de tempo de execução, em comparação ao uso de memória compartilhada e Lucas / Abstract: As processors design shift towards multicore architectures, new challenges arise to increase the core to core communication efficiency. Despite the potential huge performance impact, the number of papers focusing on this problem is limited. In this project, we define a communication model, adding three new instructions to the SPARCv8 instruction set, to allow different cores to communicate directly, without the shared memory and lock latencies. We implemented the model inside the LEON3 VHDL and evaluated it using synthetic benchmarks like producer-consumer and pipeline. To make the FPGA prototype timings more realistic, we also implemented a new memory timer so that it keeps the processor-memory speed ratio closer to real values. We also created the basic compiler support for these new instructions through intrinsic, converted to inline assembly in C code. Our overall results improve the performance from 3% to up to 70 times faster / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems. Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications. While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency. This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies.

Partial scan paths improve the testability of digital circuits, and incur minimal costs in the area overhead and test application time. Design constraints may require that a partial scan path include only those flip-flops that provide the greatest improvements in circuit testability. STAFFS, a tool that identifies such flip-flops, has been developed. It uses a statistical testability measure to acquire quantitative data for the controllabilities and observabilities of the nodes of a circuit. It predicts the changes that would occur in the data due to the scanning of specific flip-flops, and uses those predictions to select flip-flops. STAFFS weights the observability data versus the controllability data when selecting flip-flops, and it can efficiently select alternative scan designs for different weights. Experimental results for thirteen sequential benchmark circuits reveal that STAFFS consistently selects scan designs with fault coverages that are significantly higher than those of arbitrarily selected scan designs. / Master of Science

Modeling is an essential step in the design of digital circuits [71. The coding of behavioral models for complex devices is a labor intensive task. Even with the use of a to01like the "Modeler's Assistant" [4}, the development of behavioral models is time consuming and labor intensive. The use of re-usable code along with a tool like the Modeler's Assistant can speed up model development. This thesis defines a set of higher level primitives which can be used for this purpose. These primitives are built as a macro library into the tool. The Modeler's Assistant together with the modeling primitives provides us with a tool that can simplify the process of model development. / Master of Science

In this dissertation, we consider analytic and numeric approaches to the solution of probabilistic steady-state problems with specific applications in simulation and queueing theory. Our first objective on steady-state simulations is to develop new estimators for the variance parameter of a selected output process that have better performance than certain existing variance estimators in the literature. To complete our analysis of these new variance estimators, called linear combinations of overlapping variance estimators, we do the following: establish theoretical asymptotic properties of the new estimators; test the theoretical results on a battery of examples to see how the new estimators perform in practice; and use the estimators for confidence interval estimation for both the mean and the variance parameter. Our theoretical and empirical results indicate the new estimators' potential for improvements in accuracy and computational efficiency. Our second objective on steady-state simulations is to derive the expected values of various competing estimators for the variance parameter. In this research, we do the following: formulate the machinery to calculate the exact expected value of a given estimator for the variance parameter; calculate the exact expected values of various variance estimators in the literature; compute these expected values for certain stochastic processes with complicated covariance functions; and derive expressions for the mean squared error of the estimators studied herein. We find that certain standardized time series estimators outperform their competitors as the sample size becomes large. Our research on queueing theory focuses on pricing of the service provided to individual customers in a queueing system. We find sensitivity results that enable efficient computational procedures for dynamic pricing decisions for maximizing the long-run average reward in a queueing facility with the following properties: there are a fixed number of servers, each with the same constant service rate; the system has a fixed finite capacity; the price charged to a customer entering the system depends on the number of customers in the system; and the customer arrival rate depends on the current price of the service. We show that the sensitivity results considered significantly reduce the computational requirements for finding the optimal pricing policies.

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