Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, Delta-Sigma Analog-to-Digital converter in monolithic form. Autocalibration gives endpoint correction, and chopper stabilization minimizes the effect of parameter shifts, drift, and flicker noise. A digital filter, needed for all Delta-Sigma converters, serves as a signal processor to reject out-of-band noise and resonant responses of the external system. A 3-micron, double-poly CMOS process is used. Power requirements are +/- 5 Volts. A six-pole Gaussian IIR digital filter is chosen for good transient response and no overshoot. The filter algorithm and hardware solve the difference equations of a low-pass switched-capacitor prototype filter in digital form. Due to the low bandwidth needed, an area-efficient shift-and-add architecture is used. The area is further reduced with a novel multiplication algorithm, and the logic is reused to perform the calculations required for calibration. The system level device performance is verified in FORTRAN. The analog subcircuits are simulated over process and temperature corners in HSPICE. Measurements show differential and integral linearlity, DC accuracy and noise near the 20-bit level. Power supply rejection, and out-of-band signal attenuation are good, and the step response is monotonic. The circuit is marketed as Crystal Semiconductor CSC5503 and CSC5501 (20 and 16-bit resolutions, respectively).

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / Chart recorders currently in use on telemetry ranges are connected to telemetry processors via a series of Digital to Analog Converters (DAC) systems. A new modular interface system receives data directly from the processor broadcast bus and distributes them to up to ten digital chart recorders. This interface is programmed from a computer to assign individual tags to each one of the display channels. This system eliminates DAC's and patch panels. It simplifies display system operation, speeds up transition from test to test and reduces maintenance costs.

Tang, Xian. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is then analyzed. Various techniques dealing with the DAC error are described and their drawbacks are pointed out. Based on the nature of the DAC error and the surrounding signals, a fully digital method to estimate the error from the ADC output and remove it is proposed. Simulation results are shown to support the effectiveness of the method. Simulations also show that the proposed technique can work together with the technique of adaptive compensation for quantization noise leakage in cascaded delta sigma (MASH) ADC cases. These two techniques are the foundation for the design of high speed, high resolution delta sigma ADCs with relaxed requirements on the analog circuits. To verify the proposed technique, an experimental MASH ADC was built, including the design and fabrication of a chip of a second-order multi-bit delta sigma ADC in a 1.6��m CMOS technology. The measured results show that the proposed DAC correction technique is highly effective. / Graduation date: 2004

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Most delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback, the use of multi-bit quantization would improve a delta-sigma modulator's performance by increasing the modulator's resolution or increasing the modulators's bandwidth, while at the same time whitening the quantization noise and improving modulator stability. This thesis explores the element-mismatch-shaping technique, which attenuates the noise caused by static element mismatch in a multi-level DAC by a method similar to delta-sigma modulation. Existing element-matching techniques are reviewed and some analytical and architectural work related to the realization of mismatch-shaping logic is presented. A custom switched-capacitor (SC) DAC is used to verify various element mismatch-shaping algorithms. Experiments show that mismatch-shaping can reduce harmonic distortion by up to 30 dB. / Graduation date: 1998

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instruments which convert IF, or even RF, analog signals directly to digital form. This thesis presents a method used to analyze and synthesize continuous-time delta-sigma modulators for given specifications. A fourth-order prototype continuous-time bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on a PCB board and measurement results corroborate the theory. To allow the construction of very high performance delta-sigma modulators, this thesis presents an architecture for a multibit DAC constructed from unit elements which shapes element mismatches. Theoretical analysis and simulation shows that this architecture greatly increases the noise attenuation in the band-of-interest and facilitates the use of multibit quantization in delta-sigma modulators. The methods presented in this thesis will allow high-frequency wideband bandpass delta-sigma modulators to be constructed. / Graduation date: 1996

Thesis (Ph. D.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 74-75). Also available on the World Wide Web.

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