Yes / In this paper we describe a novel concept for classification of complex parametric geometry based on the concept of the Divider Set. The Divider Set is an alternative concept to maximal disks, Voronoi sets and cut loci. The Divider Set is based on a formal definition relating to topology and differential geometry. In this paper firstly we discuss the formal definition of the Divider Set for complex 3-dimensional geometry. This is then followed by the introduction of a computationally feasible algorithm for computing the Divider Set for geometry which can be defined in explicit parametric form. Thus, an explicit solution form taking advantage of the special form of the parametric geometry is presented. We also show how the Divider Set can be computed for various complex parametric geometry by means of illustrating our concept through a number of examples

Power dividers are vital components and widely used in radio technology, such as antenna arrays, power amplifiers, multiplexers and mixers. A good example is the well-known Wilkinson power divider with its distinctive feeding network characteristics. A comprehensive review indicated that limited research is carried out in the area of planar multiport and reconfigurable power dividers in terms of the power levels between output ports. The main objectives of this work were to develop a small size power divider, a planer multi-output ports power divider and a power divider with a reconfigurable power division ratio. These power dividers were designed to operate over either an ultra-wideband frequency (3.1-10.6 GHz) or WLAN bands (2.4 or 5.2 GHz). A novel multi-layered topology solved the complexity of interconnecting isolation resistors by introducing an additional layer below the ground layer. The prototype was fabricated and tested to validate the results. The measurements and simulation were in good agreement. Finally, a novel uniplanar power divider with reconfigurable output power level difference was developed. The configurability feature was achieved by tuning the quarter wave transformer using one varactor diode. The power divider was applied to improve a full duplex system cancellation performance at the receiver element caused by interference from in-site transmitting antennas. This study investigated fixed power dividers, multi-output power dividers and reconfigurable power dividers. The measurements validated by the simulation results and applications proved the designed power dividers could be used in practical applications. / Higher Committee for Education Development (HCED), Iraq

Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / This thesis elaborates on the theory and art of the design of two key RF radio hardware subsystems: analog Frequency Dividers and Low Noise Amplifiers (LNAs). Specifically, the design and analysis of two Injection Locked Frequency Dividers (ILFDs), one Regenerative Frequency Divider (RFD), and two different LNAs are documented. In addition to deriving equations for various performance metrics and topology-specific optimization criterion, measurement data and software simulations are presented to quantify several parameters of interest. Also, a study of the design of LNAs is discussed, based on three “regimes:” impedance matching, transconductance-boosting, and active noise cancelling (ANC). For the ILFDs, a study of injection-locked synchronization and phase noise reduction is offered, based on previous works. As the need for low power, high frequency radio devices continues to be driven by the mobile phone industry, Frequency Dividers that are used as prescalars in phase locked loop frequency synthesizers (PLLs) must too become capable of operation at higher frequencies while consuming little power. Not only should they be low power devices, but a wide “Locking Range” (LR) is also desired. The LR is the bandwidth of signals that a Frequency Divider is capable of dividing. As such, this thesis documents the design and analysis of two ILFDs: a Tail-ILFD and a Quench-ILFD. Both of these ILFDs are implemented on the same oscillator circuit, which consumes 2.28 mW, nominally. Measurements of the Tail and Quench-ILFDs’ LRs are plotted, including one representing the Quench-ILFD operating at “very low” power. Also, an RFD is detailed in this thesis, which consumes 410 μW. This thesis documents Locking Ranges for the Tail and Quench-ILFDs of 12% and 3.7% of 6.4 GHz respectively, during nominal operation. In “very low” power mode, the Quench-ILFD has a LR of 4.8% while consuming 219.6 μW of power. For the RFD, simulations report a LR of 16.7% while consuming 410 μW. Recently in 2011, a wideband LNA topology by Nozahi et al., which employs Partial Noise Cancelling (PNC) of the thermal noise generated by active devices, was presented and claimed to achieve a minimum and maximum NF of 1.4 dB and 1.7 dB (from 100 MHz to 2.3 GHz), while consuming 18 mW from a 1.8 V supply. This thesis details the theory, design, and simulation results of a narrowband version of this PNC LNA. In order to compare the largesignal performance of this narrowband LNA to that of a well-known implementation, an LNA employing inductive source-degeneration (referred to as a “S-L LNA”) is designed and analyzed through simulation. The PNC LNA operates at a frequency of 2.3 GHz while the S-L LNA operates at 2.8 GHz. Simulations report a NF of 1.76 dB for the PNC LNA and 2.3 dB for the SL LNA, at their respective operating frequencies. Both LNAs consume roughly 15 mW of quiescent power from a 1.8 V supply. Lastly, a case for the suspected design and layout faults, which caused fabricated versions of the RFD and two LNAs documented in this thesis to fail, is presented. First, measurements of the two LNAs are shown, which display the input impedance of the S-L LNA and the s₂₁ responses for both. Then, general layout concerns are addressed, followed by topology-specific circuit design flaws.

Create an INSIDE environment in relation to an OUTSIDE space.What gives the feeling of being inside and what outside? How much is needed in order to make an open environment close?The aim is to design a space divider for outdoor spaces. A textile flexible surface made not only for separation but also meant to be used as wind shelter, sunshades or as space organizer during happenings.From this concept to two different textile expressions and solutions: a 3 layers curtain where the juxtaposition of layers creates different atmospheres and transparencies and a one piece cutout divider, which creates spaces.‘A project which explores the relationship between architecture and the textiles solutions in outside environments, where the rigidity of architectonic shapes meets fabrics soft expressions.’ / Program: Konstnärligt masterprogram i mode- och textildesign

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The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

This thesis focuses on the Binary Integer Modulo-Division Algorithm that is essential for the permutation process in Sunar-Koc ONB Type II Multiplier and also for other general purposes. This thesis explains the new algorithm developed based on the systolic array architecture which gives a systematic approach to the iterative process for the Modulo-Division. The scheduling and projection timing functions are proposed for the processor array allocation and the matlab code has been implemented to verify the efficiency of the algorithm. The thesis also explores the possibility of word based algorithm for design optimisation. / Graduate / 0544 / 0984 / m.shubha8@gmail.com