The research focused on evaluating the feasibility into Microwave Monolithic Integrated Circuits (MMIC) fabrication capability, in the UK, using novel material type: all ternary In0.52Al0.48As/In0.53Ga0.47As lattice matched to InP substrate double heterojunction bipolar transistor (DHBT) technology; with the potential for providing high speed HBTs. The demonstration of a MMIC capability would follow with the development of a BiFET process that would satisfy SELEX Galileo circuit business needs. The research project complexity is divide into 5 phases: phase 1, the development of a high frequency In0.52Al0.48As / In0.53Ga0.47As lattice matched to InP substrate DHBT technology; phase 2, development of passive components; phase 3, the creation of two VBIC physical models; phase 4, the creation of a Process Development Kit (PDK) and phase 5, the design, simulation and fabrication of a divide-by-2 frequency divider using the technology developed in phase 1. Phase 1, concluded with a DHBT epitaxial design and fabrication that produced devices with a peak high frequency performance f_t = 140GHz and f_max = 95GHz at a current density Jc ≈ 1mA/µm2. This was achieved through the optimisation of the epitaxial design to reduce the base transit time τb through the introduction of a quasi electric field and thinning of base layer. To the best of the author’s knowledge, this is the highest f_t performance for a 1µm emitter width all ternary In0.52Al0.48As / In0.53Ga0.47As DHBT. The design, simulation and fabrication of a divide-by-2 frequency divider were only made possible by the successfully development of passive components (phase 2) and the VBIC model and PDK creation (phase 3 and 4). The divide-by-2 frequency divider design and simulation was done via the use of the PDK. The simulations resulted in a divide-by-2 frequency divider with a maximum operating frequency of 27GHz at a minimum input power of 2dBm. The fabrication of the MMIC resulted in a transistor component yield of 69%, which unfortunately resulted in a divide-by-2 frequency divider circuit yield of 0%. The fabrication of MMIC circuits is not possible with current state of the fabrication environment; however the only obstacle the University of Manchester (UoM) faces is low active component yield. To increase the active component yield to the 95% level required for high circuit yields, large capital investment into the fabrication equipment and human time into setting up the fabrication process to a repeatable and reliable standard is required.

This diploma thesis deals with optical and optoelectronic components. The first part describes three selected optical and three optoelectronic components. Optical components include power divider, isolator and circulator. The optoelectronic ones are laser diode, photodetector and modulator. Basic measurement parameters were defined for each component. In the experimental part, four components from different manufacturers were measured. Selected components are power dividers, isolators, circulators and a laser diode. Subsequently, the measured parameters were compared with the catalog values.

No / The design of a physically small, equal phase and equal power, 1-to-4 ultra-wideband Wilkinson power divider is presented. Initially, a 1-to-2 divider was designed and optimized for the 3.1 GHz-to-10.6 GHz range. The 1-to-4 divider was then realized using three 1-to-2 dividers, and further optimized for full band insertion loss, return loss, and isolation. The circuits were constructed using a 0.75 mm thick Rogers RO3035 substrate, and experimentally validated.

Yes / A novel beam-forming module based on Wilkinson power divider technology, including attenuators and phase shifter chips is designed, fabricated and evaluated to be incorporated in a Relay Station connecting it with the Base Station under a 4G network. The proposed module is a 1:8 port circuit, utilizing two substrates, providing approximately 700 MHz bandwidth over 3.5 GHz frequency band and less than −20 dB transmission line coupling. Moreover an external control unit that feeds the beam-forming module with code-words that define the proper amplitude/phase of the excitation currents is established and described. The presented module is connected to a planar array and tested for two beam-forming scenarios, providing satisfactory radiation patterns.

Multi band technology helps in getting multiple operating frequencies using a single microwave device. This thesis presents the design of dual and tri band microwave devices using coupled transmission line structures. Chapter 2 presents the design of a novel dual band transmission line structure using coupled lines. In chapter 3, Design of a dual band branch line coupler and a dual band Wilkinson power divider are proposed using the novel dual band transmission line structure presented in the previous chapter. In chapter 4, Design of a tri band transmission line structure by extending the dual band structure is presented. The Conclusion and future work are presented in chapter 5.

La synthèse de fréquences est une fonction largement utilisée dans les émetteur-récepteurs radios. En général, la fonction synthèse de fréquence est réalisée à l’aide d’une boucle à verrouillage de phase utilisant des diviseurs de fréquence numériques. Cette thèse présente un nouveau type de diviseur de fréquence faisant appel à des mémoires D et son application à la synthèse de fréquences. Ce nouveau diviseur permet de repousser les limites des diviseurs numériques classiques à bascules D, en matière de fréquence maximale de fonctionnement et de consommation, tout en conservant leur souplesse d’utilisation. La première partie de cette thèse présente les techniques usuelles de réalisation des synthèses de fréquence et des diviseurs de fréquences, ainsi que le nouveau diviseur SRO à base de mémoires D, sujet de ces travaux. Une étude détaillée de ce diviseur est réalisée avec un premier modèle utilisant une approche numérique, puis un second plus réaliste faisant appel à une modélisation de type analogique. Cette étude démontre que ce nouveau diviseur SRO est capable de fonctionner à une fréquence plus élevée ou avec une consommation moindre, tout en réalisant les mêmes facteurs de division, que les diviseurs classiques à bascules D. La dernière partie de cette thèse présente plusieurs implémentations en technologies CMOS et BiCMOS de ST Microelectronics du diviseur SRO. En particulier son implémentation dans deux synthétiseurs de fréquences fractionnaires à 24 GHz montre son intérêt de part la réduction significative de consommation obtenue, tout en conservant une structure simple utilisant une surface de silicium réduite / Frequency synthesis is almost used in all RF transceivers, where this function is usually achieved by using phase-locked-loop circuits. Most often, the phase-locked-loop includes digital frequency dividers in the feedback that present high power dissipation and low maximum frequency at gigahertz frequencies. This thesis presents a versatile new D latch-based divider that improves these issues and its application to frequency synthesis. The first part presents several frequency synthesis techniques and theirs main characteristics. Then is described various classical frequency dividers and the proposed new D latch-based SRO divider. A detailed study of the SRO divider is presented with two approaches, the digital one and the analogue one. This study demonstrates the benefit of the SRO divider in terms of power dissipation and speed compared with the widely used D flip-flop based dividers. The last part presents several implementations of the SRO divider in CMOS and BiCMOS processes of ST Microelectronics. Particularly, the SRO divider was implemented in two 24 GHz fractional synthesizers, where it demonstrates its interest for reduction of power dissipation while using small silicon area.

Title: 100 m hurdle race women in fire sport. Objectives: A description of the discipline of 100 m hurdle race women and a description of rendition technique from the methodical point of view is the main objective of this work. Methods: A descriptive method and a video record analysis were used in this work. Each phases are slowed-motion and retroactive described. Results: It`s a methodical description of the discipline with the video record and it will be used for coaching purposes for beginning and also advanced racers. It will improve technique of 100 m hurdle race and also achieve better sports performances too. Keywords: run, start, hurdle, beam, fire divider, technique, movement, analysis.

In asymmetric cryptosystems, an important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key lengths than other cryptosystems. It can provide a level of security when the bit length over than 160 bits. So it has become a popular public key cryptographic system in recent year. Multiplier needs to run many times in scalar multiplication and it plays an essential role in ECC. Since the registers in multiplier are shifted every iteration, it will consume a lot of power in the computing process. So in this thesis, we propose five methods to save multiplication¡¦s energy consumption based on a scalable serial-parallel algorithm[1]. The first method is to design a low-power shift-register by modifying shift-register B to reduce the frequency of registers shifted. The second method is to use a frequency divider circuit. It can make registers to access a value every two clock cycles by modifying RA units. The third method is to introduce the gated clock circuit, and the clock signal of register will be disabled if its value is the same. The fourth method is to skip redundant operations and it can decrease the number of clock cycles for completing a multiplication operation. The last method raises multiplier¡¦s throughput by modifying RA units. The former three methods focus on low-power design, and the latter two methods emphasize on improving performance. Reducing power consumption and improving performance will save multiplication¡¦s energy consumption. Finally, we propose a Half Cycles schedule to raise scalar multiplication¡¦s performance. It is based on Montgomery scalar multiplication algorithm with projective coordinate[22][26]. For the hardware implementation, TSMC 0.13um library is employed and all modules are organized in a hierarchy structure. The implementation results show that the proposed multipliers have less energy consumption than traditional multiplier. It can get 5% ~ 24% energy saving. For Montgomery scalar multiplication, it can also reduce 12% ~ 47% energy consumption and is suitable for portable electronic products because its low area complexity and low energy.

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.