Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / This thesis elaborates on the theory and art of the design of two key RF radio hardware subsystems: analog Frequency Dividers and Low Noise Amplifiers (LNAs). Specifically, the design and analysis of two Injection Locked Frequency Dividers (ILFDs), one Regenerative Frequency Divider (RFD), and two different LNAs are documented. In addition to deriving equations for various performance metrics and topology-specific optimization criterion, measurement data and software simulations are presented to quantify several parameters of interest. Also, a study of the design of LNAs is discussed, based on three “regimes:” impedance matching, transconductance-boosting, and active noise cancelling (ANC). For the ILFDs, a study of injection-locked synchronization and phase noise reduction is offered, based on previous works. As the need for low power, high frequency radio devices continues to be driven by the mobile phone industry, Frequency Dividers that are used as prescalars in phase locked loop frequency synthesizers (PLLs) must too become capable of operation at higher frequencies while consuming little power. Not only should they be low power devices, but a wide “Locking Range” (LR) is also desired. The LR is the bandwidth of signals that a Frequency Divider is capable of dividing. As such, this thesis documents the design and analysis of two ILFDs: a Tail-ILFD and a Quench-ILFD. Both of these ILFDs are implemented on the same oscillator circuit, which consumes 2.28 mW, nominally. Measurements of the Tail and Quench-ILFDs’ LRs are plotted, including one representing the Quench-ILFD operating at “very low” power. Also, an RFD is detailed in this thesis, which consumes 410 μW. This thesis documents Locking Ranges for the Tail and Quench-ILFDs of 12% and 3.7% of 6.4 GHz respectively, during nominal operation. In “very low” power mode, the Quench-ILFD has a LR of 4.8% while consuming 219.6 μW of power. For the RFD, simulations report a LR of 16.7% while consuming 410 μW. Recently in 2011, a wideband LNA topology by Nozahi et al., which employs Partial Noise Cancelling (PNC) of the thermal noise generated by active devices, was presented and claimed to achieve a minimum and maximum NF of 1.4 dB and 1.7 dB (from 100 MHz to 2.3 GHz), while consuming 18 mW from a 1.8 V supply. This thesis details the theory, design, and simulation results of a narrowband version of this PNC LNA. In order to compare the largesignal performance of this narrowband LNA to that of a well-known implementation, an LNA employing inductive source-degeneration (referred to as a “S-L LNA”) is designed and analyzed through simulation. The PNC LNA operates at a frequency of 2.3 GHz while the S-L LNA operates at 2.8 GHz. Simulations report a NF of 1.76 dB for the PNC LNA and 2.3 dB for the SL LNA, at their respective operating frequencies. Both LNAs consume roughly 15 mW of quiescent power from a 1.8 V supply. Lastly, a case for the suspected design and layout faults, which caused fabricated versions of the RFD and two LNAs documented in this thesis to fail, is presented. First, measurements of the two LNAs are shown, which display the input impedance of the S-L LNA and the s₂₁ responses for both. Then, general layout concerns are addressed, followed by topology-specific circuit design flaws.

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The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

<p>This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden. </p><p>The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project. </p><p>A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report. </p><p>The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.</p>

This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden. The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project. A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report. The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.

The research focused on evaluating the feasibility into Microwave Monolithic Integrated Circuits (MMIC) fabrication capability, in the UK, using novel material type: all ternary In0.52Al0.48As/In0.53Ga0.47As lattice matched to InP substrate double heterojunction bipolar transistor (DHBT) technology; with the potential for providing high speed HBTs. The demonstration of a MMIC capability would follow with the development of a BiFET process that would satisfy SELEX Galileo circuit business needs. The research project complexity is divide into 5 phases: phase 1, the development of a high frequency In0.52Al0.48As / In0.53Ga0.47As lattice matched to InP substrate DHBT technology; phase 2, development of passive components; phase 3, the creation of two VBIC physical models; phase 4, the creation of a Process Development Kit (PDK) and phase 5, the design, simulation and fabrication of a divide-by-2 frequency divider using the technology developed in phase 1. Phase 1, concluded with a DHBT epitaxial design and fabrication that produced devices with a peak high frequency performance f_t = 140GHz and f_max = 95GHz at a current density Jc ≈ 1mA/µm2. This was achieved through the optimisation of the epitaxial design to reduce the base transit time τb through the introduction of a quasi electric field and thinning of base layer. To the best of the author’s knowledge, this is the highest f_t performance for a 1µm emitter width all ternary In0.52Al0.48As / In0.53Ga0.47As DHBT. The design, simulation and fabrication of a divide-by-2 frequency divider were only made possible by the successfully development of passive components (phase 2) and the VBIC model and PDK creation (phase 3 and 4). The divide-by-2 frequency divider design and simulation was done via the use of the PDK. The simulations resulted in a divide-by-2 frequency divider with a maximum operating frequency of 27GHz at a minimum input power of 2dBm. The fabrication of the MMIC resulted in a transistor component yield of 69%, which unfortunately resulted in a divide-by-2 frequency divider circuit yield of 0%. The fabrication of MMIC circuits is not possible with current state of the fabrication environment; however the only obstacle the University of Manchester (UoM) faces is low active component yield. To increase the active component yield to the 95% level required for high circuit yields, large capital investment into the fabrication equipment and human time into setting up the fabrication process to a repeatable and reliable standard is required.

La synthèse de fréquences est une fonction largement utilisée dans les émetteur-récepteurs radios. En général, la fonction synthèse de fréquence est réalisée à l’aide d’une boucle à verrouillage de phase utilisant des diviseurs de fréquence numériques. Cette thèse présente un nouveau type de diviseur de fréquence faisant appel à des mémoires D et son application à la synthèse de fréquences. Ce nouveau diviseur permet de repousser les limites des diviseurs numériques classiques à bascules D, en matière de fréquence maximale de fonctionnement et de consommation, tout en conservant leur souplesse d’utilisation. La première partie de cette thèse présente les techniques usuelles de réalisation des synthèses de fréquence et des diviseurs de fréquences, ainsi que le nouveau diviseur SRO à base de mémoires D, sujet de ces travaux. Une étude détaillée de ce diviseur est réalisée avec un premier modèle utilisant une approche numérique, puis un second plus réaliste faisant appel à une modélisation de type analogique. Cette étude démontre que ce nouveau diviseur SRO est capable de fonctionner à une fréquence plus élevée ou avec une consommation moindre, tout en réalisant les mêmes facteurs de division, que les diviseurs classiques à bascules D. La dernière partie de cette thèse présente plusieurs implémentations en technologies CMOS et BiCMOS de ST Microelectronics du diviseur SRO. En particulier son implémentation dans deux synthétiseurs de fréquences fractionnaires à 24 GHz montre son intérêt de part la réduction significative de consommation obtenue, tout en conservant une structure simple utilisant une surface de silicium réduite / Frequency synthesis is almost used in all RF transceivers, where this function is usually achieved by using phase-locked-loop circuits. Most often, the phase-locked-loop includes digital frequency dividers in the feedback that present high power dissipation and low maximum frequency at gigahertz frequencies. This thesis presents a versatile new D latch-based divider that improves these issues and its application to frequency synthesis. The first part presents several frequency synthesis techniques and theirs main characteristics. Then is described various classical frequency dividers and the proposed new D latch-based SRO divider. A detailed study of the SRO divider is presented with two approaches, the digital one and the analogue one. This study demonstrates the benefit of the SRO divider in terms of power dissipation and speed compared with the widely used D flip-flop based dividers. The last part presents several implementations of the SRO divider in CMOS and BiCMOS processes of ST Microelectronics. Particularly, the SRO divider was implemented in two 24 GHz fractional synthesizers, where it demonstrates its interest for reduction of power dissipation while using small silicon area.

In asymmetric cryptosystems, an important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key lengths than other cryptosystems. It can provide a level of security when the bit length over than 160 bits. So it has become a popular public key cryptographic system in recent year. Multiplier needs to run many times in scalar multiplication and it plays an essential role in ECC. Since the registers in multiplier are shifted every iteration, it will consume a lot of power in the computing process. So in this thesis, we propose five methods to save multiplication¡¦s energy consumption based on a scalable serial-parallel algorithm[1]. The first method is to design a low-power shift-register by modifying shift-register B to reduce the frequency of registers shifted. The second method is to use a frequency divider circuit. It can make registers to access a value every two clock cycles by modifying RA units. The third method is to introduce the gated clock circuit, and the clock signal of register will be disabled if its value is the same. The fourth method is to skip redundant operations and it can decrease the number of clock cycles for completing a multiplication operation. The last method raises multiplier¡¦s throughput by modifying RA units. The former three methods focus on low-power design, and the latter two methods emphasize on improving performance. Reducing power consumption and improving performance will save multiplication¡¦s energy consumption. Finally, we propose a Half Cycles schedule to raise scalar multiplication¡¦s performance. It is based on Montgomery scalar multiplication algorithm with projective coordinate[22][26]. For the hardware implementation, TSMC 0.13um library is employed and all modules are organized in a hierarchy structure. The implementation results show that the proposed multipliers have less energy consumption than traditional multiplier. It can get 5% ~ 24% energy saving. For Montgomery scalar multiplication, it can also reduce 12% ~ 47% energy consumption and is suitable for portable electronic products because its low area complexity and low energy.

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.

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