The increase in the occurrence of non-linear loads in power systems has caused considerable concern to power utilities and manufacturers of power electronics equipment. To alleviate the problems caused by generation of current harmonics, there has been considerable interest in the use of active filters. This thesis presents a unified approach to the design of active filter configurations. It is shown that this approach offers a systematic method of classifying existing structures and it can be used for developing new circuits.

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later.

No description available.

The Equipment Controls and Electronics section (EN-STI-ECE) at CERN is developing a high precision piezo-actuated rotational stage for the UA9 crystal collimation project. This collaboration is investigating how tiny bent crystals can help to steer particle beams used in modern hadron colliders such as the Large Hadron Collider (LHC). Particles are deflected by following the crystal planar channels, "channeling" through the crystal. For high energy particles the angular acceptance for channeling is very low, demanding for a high angular precision mechanism, i.e. the rotational stage. Several control-related issues arising from the complexity and operational environment of the system make it difficult to design a controller that achieves the desired performance. This thesis investigates different control approaches that could be used to improve the tracking capability of the rotational stage. It shows that the IRC method could be used to efficiently control the rotational stage. Moreover it shows that a harmonic cancellation method could be used to increase the tracking accuracy by canceling known harmonic disturbances. The harmonic cancellation method (the RFDC) was implemented in this thesis and proposed as an add-on to the present control algorithm.

Développer un générateur de signal analogique efficace est un élément clés pour les BIST des circuits analogiques et mixtes afin de produire le stimulus de test approprié, et remplacer les générateurs de signaux externes couteux dans les protocoles de standard de test fonctionnel analogique et mixte. Dans cette optique, nous présentons dans cette thèse des stratégies différentes de génération de signal sinusoïdal, basées sur les techniques d’annulation d’harmonique, pour le design d’un synthétiseur embarqué de signal sinusoïdal à haute fréquence. Les générateurs proposés utilisent des circuits numériques pour produire un ensemble de signaux carrés déphasés. Ces signaux carrés sont pondérés et combinés en appliquant différentes stratégies d’annulation d’harmonique dans un convertisseur numérique-analogique simplifié. Le générateur sélectionné permet d’annuler toutes les harmoniques en dessous de la 11ème. De plus, une simple stratégie de calibration a été conçue pour compenser l’effet de mismatch et de la variation de process de fabrication sur l’efficacité de la technique d’annulation d’harmonique. La simplicité du circuit rend cette approche adaptable pour le BIST des circuits intégrés analogique et mixte. Les modèles comportementaux, les simulations électriques d’un design en 28nm FDSOI et les résultats expérimentaux sont fournis pour valider la fonctionnalité du générateur proposé. Les résultats obtenus montrent des performances du circuit calibré autour de 52dB de SFDR pour un signal généré à 166MHz. / One of the main key points to enable mixed-signal BIST solutions is the development of efficient on-chip analog signal generators that can provide appropriate test stimuli and replace costly external signal generators in standard analog and mixed-signal functional test protocols. In this line, we present in this thesis different sinewave generation strategies based on harmonic cancellation techniques to design a high-frequency on-chip sinusoidal synthetize. The proposed generators employ digital hardware to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using different harmonic cancellation strategies in a simplified current-steering DAC. The selected generator allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28nm FDSOI design and experimental results are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 52dB of SFDR for a generated sinusoidal signal at 166 MHz.

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.