<div>Driving safety is a very important topic in vehicle development. One of the biggest threat of driving safety is road departure. Many vehicle active safety technologies have been developed to warn and mitigate road departure in recent years. In order to evaluate the performance of road departure warning and mitigation technologies, the standard testing environment need to be developed. The testing environment shall be standardized to provide consistent and repeatable features in various locations worldwide and in various seasons. The testing environment should also be safe to the vehicle under test in case the safety features do not function well. Therefore, soft, durable and reusable surrogates of roadside objects need to be used. Meanwhile, all surrogates should have the same representative characteristics of real roadside objects to different automotive sensors (e.g. radar, LIDAR and camera). This thesis describes the study on identifying the radar characteristics of common roadside objects, metal guardrail, grass, and concrete divider, and the development of the required radar characteristics of surrogate objects. The whole process is divided into two steps. The first step is to find the proper methods to measure the radar properties of those three roadside objects. The measurement result of each roadside object will be used as the requirement for making its surrogate. The second step is to create the material for developing the surrogate of each roadside object. In the experimental results demonstrate that all three surrogates satisfy their radar characteristics requirements.</div>

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

The thesis paper Design takes place in our lives, naturally and sometimes invisibly, but how can we become alert to its impact on us? How can we as designers elaborate on our role in creating tools for people’s lives? A handmade metal wire toy I found in my parents’ house made me discover the world of mandalas; a Buddhistic symbol and a tool for spiritual enlightenment. Mandalas speak of the relation between us and the world and balance between body and mind. In my Master’s project, the act of playing is explored as a tool for altering perspectives on our physical environment. Inspired by the mandala, an alternative approach to functional form is visualized, connecting our bodies and minds in closer relation to a playful and imaginative state of being. By investigating our physical environment and encouraging interaction, new mantras for our everyday lives may be created. The design process Using the metal wire mandala as my starting point, I have explored spatial forms with possibilities in transformation. Different combinations of the same parts; half circles of bent metal wire which connected can move and therefore change the other shape of the construction, creates different kinds of space with more or less clear practical application. The ambition of this project has been to investigate the metal construction as foundation and frame for textile in and as architecture; building a whole space, as visual room dividers indoor or outdoor and as sun screen. The design is based on transformation and reuse of the same parts to build new forms. The textiles have been designed and produced with the metal construction as frame. The textiles are knitted with nylon thread, hand dyed and mounted onto the construction. The technique of partial knitting makes it possible to create the round shapes with an even elasticity in all directions, and an open centre for the next piece overlapping. When knitting, no waste material I generated since nothing is cut away after production. Using punch cards, patterns and structure is added to the surface. The need to create smaller spaces within a larger space is present in many places; indoors as well as out doors. The public environment in which we live, controls and shapes our lives. By creating more intimate sites, with the possibility for visual and mental rest, we can come closer one another and hold other types of conversations. This will create new patterns of behaviour; new mantras for everyday life. During the Konstfack Degree Exhibition 2013, I displayed one of the possible forms in full scale with textiles, along side a smaller size model of the same shape and one other possible shape with closer resemblance to the original wire toy. On site in the exhibition, visitors could meet and try the space in a real setting. / Thesis uppsats Formgivning sker i våra liv, naturligt och ibland osynligt, men hur kan vi bli uppmärksamma på dess inverkan på oss? Hur kan vi som formgivare utveckla vår roll i att skapa redskap för människors liv? En handgjord leksak av metalltråd som jag hittade i mitt föräldrahem fick mig att upptäcka mandalans värld – en buddistisk symbol och ett redskap för andlig upplysning. Mandalan vittnar om förhållandet mellan oss och världen och jämvikt mellan kropp och själ. I mitt masterarbete utforskas lekaktivitet som ett redskap för att ändra perspektiv på vår fysiska omgivning. Med inspiration från mandalan åskådliggörs en alternativ infallsvinkel på funktionell form som förenar våra kroppar och sinnen mer intimt med en lekfull och fantasifull tillvaro. Genom att undersöka vår fysiska omgivning och uppmuntra samspel kan vi skapa nya mantra för vardagen. Designprocessen Med leksaken av metalltråd som utgångspunkt, har jag utforskat rumsliga former med möjlighet till transformation. Olika kompositioner av samma byggstenar; halvcirklar av böjd metalltråd vilka sammanlänkade kan röra sig mot varandra och på så vis förändra den yttre formen, skapar olika typer av rumsligheter med mer eller mindre definierad praktisk användning. Projektets ambition har varit att utforska metallkonstruktionens möjligheter som stomme för textil i och som arkitektur; som skapande av hela rum, som visuella rumsavdelare inomhus eller utomhus samt som solskydd. Designen bygger på förvandling och återanvändning, där samma delar kan användas till att sätta samman nya former. De textila materialen har arbetats fram med metallkonstruktionen som utgångspunkt och ram. Textilierna är stickade i nylon, färgade och monterade i konstruktionen. Tekniken att delsticka på stickmaskin möjliggör att de runda formerna med jämn elasticitet åt alla håll, och ett hål lämnas i centrum för nästa överlappande del i den monterade konstruktionen. I stickningen skapas heller inget spillmaterial eftersom ingenting klipps bort efter tillverkningen. Med hjälp av hålkort integreras mönstringar och strukturer. Behovet av att skapa mindre rum i större rum finns många platser; inomhus såväl som utomhus. De offentliga platser vi rör oss på styr vårt beteende och formar våra liv. Med intimare mötesplatser och möjlighet till visuell och mental vila kan vi komma närmare varandra och föra andra typer av samtal vilket kan skapa nya mönster av beteende; nya mantran. Under Konstfacks vårutställning 2013, visades en av de möjliga formerna i fullskala med textilier, samt en mindre modell av denna samt en annan form med tydlig anknytning till mandala-leksakens ursprungliga form. På plats i utställningen kunde besökare pröva rummet i ett verkligt sammanhang.

First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.

Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.

Cette thèse porte sur l’analyse et la conception de générateurs de fréquence millimétrique à faible bruit de phase destinés à des applications de communication sans fil de très haut débit sur une technologie BiCMOS 0.25m. Spécifiquement, des applications backhauling sont visées sur le protocole de communication P2P (point-to-point), pour un système de radio hétérodyne (à faible fréquence intermédiaire) approprié pour les bandes entre 30–38GHz et de faible profondeur de modulation (2-3 bits /symbole). Une étude rigoureuse du comportement du bruit de phase en 1/f2 d’un oscillateur contrôlé en tension (du type paire différentielle croisée) en fonction de la fréquence d’oscillation est développée. Des facteurs essentiels pour la conception de ces oscillateurs tels que la plage de fréquence et la charge de la paire croisée sur le résonateur sont pris en compte dans l’analyse. L’étude révèle que lorsque la fréquence augmente, l’oscillateur passe à travers deux régimes d’opération différents, ici appelés région QL-limited et région QC- limited, qui résultent de la dépendance du facteur de qualité du résonateur à sa partie inductive (pour les basses fréquences d’oscillation) et sa partie capacitive (pour les hautes fréquences d’oscillation). De plus, l’impact de la plage de fréquence sur l’évolution du bruit de phase en 1/f2 a été considéré en utilisant un circuit classique à base d’un varactor et d’un condensateur du type MiM. Des équations simples et précises ont été calculées pour les paramètres du circuit afin d’obtenir une fréquence centrale souhaitée avec la variation de la capacité requise. Pour ce circuit, il a été démontré (et vérifié à travers des simulations du circuit) que le pire scénario du facteur de qualité peut être associé à la constante de temps d’un condensateur. Ce dernier a permis d’estimer aisément le facteur de qualité minimal de la partie capacitive du résonateur LC de l’oscillateur, pour une plage de fréquence donnée, en fonction de la fréquence d’oscillation. D’une manière similaire, et basée sur une analyse à petit signal, la constante de temps de la capacité de sortie de la paire croisé a été déterminée. Notamment cette constante de temps présente un comportement constant sur une large gamme de fréquences, ce qui permet d’évaluer facilement son facteur de qualité. Cette étude fournit les bases théoriques qui permettent l’évaluation du bruit de phase en 1/f2 d’une source de signal basée sur un oscillateur en mode fondamental, super-harmonique ou sous-harmonique. En effet, la supériorité des oscillateurs sous-harmoniques est démontrée et des équations simples sont proposées pour déterminer la performance maximale et les conditions dans lesquelles elles peuvent être atteintes. Enfin, un système de génération de signal est ainsi conçu et vérifié par des mesures sur un prototype. Le système est composé d’un VCO sous-harmonique suivi d’un tripleur de fréquence (ILFT) –verrouillé par injection. Le circuit est implémenté sur une technologie SiGe:C BiCMOS 0.25 m. Le tripleur implémente une configuration à émetteur commun, polarisé en courant, qui exploite la seconde harmonique du VCO afin d’améliorer l’efficacité de la génération du signal responsable de verrouiller le ILFT. A 30.8 GHz, le système atteint un bruit de phase de -112 dBc/Hz à 1MHz d’offset. La consommation totale de courant est de 38mA pour une tension d’alimentation de 2.5V. Un deuxième prototype a été réalisé pour un système de génération multibande, offrant ainsi trois sorties RF à 18 GHz, 34GHz et 68 GHz. Avec une plage de fréquence de 10% (mesurée par rapport à la fréquence centrale) pour chaque sortie RF. Le bruit de phase mesuré à 1MHz d’offset est respectivement de -113dBc/Hz, -107dBc/Hz et -100dBc/Hz.. / This thesis deals with the analysis and design of Low phase Noise Local-Oscillator(LO) sources suitable for backhauling applications on the frequencies 30-38GHz. The LO is intended to be used in a low-IF architecture for low order modulations (2-3 bits/symbol). This work was developed in collaboration with NXP Semiconductorsat CAEN, France, within the project RF2THz of the European program CATRENE.The original contributions in this work include a rigorous study of the 1/f2 phasenoise characteristics of the VCO (bipolar cross-coupled pair Voltage-Controlled-Oscillator) with the oscillating frequency. Key factors in the design of VCOs such as tuning range and the tank load given by the cross-coupled pair are considered in the analysis. The study reveals that as the frequency scales, the VCO passes through two different zones, named the QL-limited and the QC-limited region, that results from the dependence of the resonator quality factor on its inductive part (for low oscillating frequencies) and its capacitive part (for high oscillating frequencies). Moreover, the impact of the tuning range on the 1/f2 phase noise evolution was captured by using a classical circuit based on an AC-coupled varactor and a MiM capacitor. Simple and accurate equations were derived for the circuit parameters in order to achieve a desired central frequency with the required capacitance variation. For this circuit, it is demonstrated (and verified through circuit simulations) that the lowest quality factor scenario can be associated to the time-constant of a lossy capacitor. The latter allows to estimate easily the minimum quality factor of the capacitive part of the VCO LC tank, for a given tuning range, as a function of the oscillating frequency. In a similar way, and based on a small signal analysis, the time-constant of the output capacitance of the bipolar cross-coupled pair was derived. Interesting, this time constant shows a constant behavior over a wide frequency range, thereby allowing to estimate easily its quality factor. This study set the bases for an analytical framework that enables the evaluation of the 1/f2 phase noise performances of local oscillator sources working either on fundamental,super-harmonic or sub-harmonic mode. The superiority in terms of 1/f2 phase noise of local oscillators based on sub-harmonic oscillators is thus demonstrated and simple equations are derived to determine the maximum performance and the conditions on which this can be achieved. Finally, a signal generation system intended for a low-IF point-to-point fixed radio system in the Ka-Band band is thus designed and verified through prototype measurements.The system is composed by a sub-harmonic VCO followed by an injectionlocked frequency tripler (ILFT) and it is designed in a 0.25m BiCMOS SiGe:C technology. The ILFT implements a cascode current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8GHz, the system achieves a phase noise of -112dBc/Hz at 1MHz offset. The total current consumption is 38mA for a supply voltage of 2.5V. A second prototype is designed for a multiband LO generation, providing thus three RF outputs at 18GHz, 34GHz and 68GHz. With a measured tuning range of 10% for each RF output, the measured phase noise at 1MHz is -113dBc/Hz, -107dBc/Hz and -100dBc/Hz respectively.

Master's thesis deals with the design of an antenna system for wireless sound transmission used mainly in professional sound reinforcement. The introductory part deals generally with wireless microphones, frequency bands used and proven antenna types. Next, this work deals with signal distribution that is realized using the antenna splitter. The antenna parts is focused on easy production and real usage, therefore were selected antennas with appropriate properties suitable for small series production. This thesis includes simulation of each device, their real construction design and measurements of built prototypes and final products. All three produced devices – the rack splitter, /4 antenna and Helix antenna are fully working, achieve good parameters and are ready for further manufacturing and easy modifications in case of frequency band change requirement. The conclusion includes an overall assessment of the results achieved.

In this master´s thesis an issue of broadband planar antennas was analyzed. Firstly, the basic elements that affect bandwidth, such as the influence of the dieletric substrate, suitable shape or feeding network, were described. Furthermore technics that can be used to widen the band of the planar antennas were described. These technics were applied to a chosen type of a planar antenna. This antenna was modeled and simulated for desired dielectric substrate in CST STUDIO SUITE 2010 software. Feeding network with power dividers was designed for the antenna array. In order to obtain a higher gain, the antenna was implemented into the 2x2 element array. The results of the simulation are evaluated in the conclusion.

Purpose of this engineer thesis is project of machine grating with hydraulic driving clearing. Diplom thesis includes construction solution of hydraulic cleaner-machine and koncept of hydraulic circuit. A part of this work is design of possible hydraulic driving and working stuffing. All hydraulic components are choosen from catalogue of appropriate companies.

This master’s thesis deals with the design of autonomous monitoring system electronics which will be used for diagnostics of the electromagnetic vibration generator developed at Brno University of Technology. This generator should be used in a practical application where frequent mechanical shocks are present, for example in vehicle or goods transportation. For such an application, the goal of the monitoring system is to find out whether generator is capable of producing enough electrical energy for smooth operation of wireless sensors used in similar applications. The first part of the thesis consists of the autonomous diagnostics system overview from both commercial and scientific spheres, brief description of the vibration generator used and also a summary of commercially available power management electronics. The next chapters present the detailed description of each functional element of energy harvesting system, the simulation of generator’s behaviour for optimal load in three different model applications and the most important part – design of the autonomous monitoring system. In the end, achieved results are evaluated and it is considered whether the shock-driven generator is suitable for use in a given application.