La réduction des dimensions des dispositifs et les limites atteintes par la lithographie pour les nœuds technologiques sub-20nm requièrent l’introduction d’un « double patterning » pour définir les contacts. Le masque final est défini par l’intersection d’un masque dur en TiN et d’un masque organique (OPL) et est utilisé pour transférer les motifs des contacts par gravure plasma dans une couche de diélectriques (SiO2/Si3N4). Par rapport aux nœuds technologiques précédents, cette architecture entraine de nouvelles problématiques dues à l’intégration du double patterning et du masque dur en TiN.Cette thèse porte sur la gravure des contacts définis par « double patterning » pour la technologie 14 nm FDSOI (Fully Depleted Silicon On Insulator) à STMicroelectronics. Plus particulièrement, l’objectif principal de ce travail de thèse a été d’évaluer l’effet des masques d’OPL et de TiN sur la gravure des contacts en termes de contrôle dimensionnel (CD) et de profil de gravure. Dans cet objectif, nous avons comparé deux procédés de gravure de l’OPL à base de N2/H2 ou de COS/O2 et leur impact sur le transfert des contacts. Un autre objectif de ce travail de thèse a été consacré à la compréhension et à la limitation du phénomène de croissance de résidus métalliques après le procédé de gravure des contacts. Ceci est obtenu notamment à travers le développement de traitements plasma post gravure. Pour déterminer les mécanismes d’interactions entre les plasmas du procédé de gravure des contacts et les matériaux des masques, des analyses de la surface des matériaux exposés aux plasmas ont été réalisées par des techniques telles que l’XPS et l’EDX et des analyses de la phase gazeuses du plasma ont été réalisées par spectroscopie d’émission optique (Optical Emission Spectroscopy – OES). Nous avons montré que les profiles des contacts étaient influencés par le procédé de l’étape d’ouverture de l’OPL et particulièrement à travers l’interaction des plasmas et du masque dur en TiN. Cette interaction peut conduire à une modification de la forme du masque dur en TiN et au redépôt de composés métalliques peu volatils sur la plaque et sur les parois du réacteur au cours du procédé de gravure. Ceci peut conduire à une déformation des profils et à un quasi-arrêt de la gravure pendant la gravure des matériaux diélectriques. Par ailleurs, nous avons montré que l’efficacité des traitements à base de méthane pour ralentir ou éviter la croissance de résidus à la surface du TiN après la gravure des diélectriques peut être améliorée par un contrôle de l’état des parois de la chambre au cours du traitement, en effectuant un nettoyage de la chambre en oxygène avant l’application du traitement. / Due to the reduction of the transistor dimensions and the limitations of the lithography to define small contact patterns for the sub-20nm technological nodes, the introduction of double patterning strategies is required for contact patterning. In such architectures, the final mask is defined by the combination of a TiN hard mask and an organic (OPL) mask, which defines the contact patterns that will be transferred into the underlying dielectric layers (SiO2/Si3N4). This leads to new challenges for contacts definition, especially because of the integration of double patterning strategies and TiN hard masks which were not present for previous technologies.This study addresses the contact etching process using a double patterning strategy for the 14 nm Fully Depleted Silicon on Insulator (FDSOI) technology. More particularly, the main goal of this work was to evaluate the impact of both TiN and OPL masks on the contact patterning process in terms of dimensions and profiles control. For this, we have compared two different OPL etch processes (N2/H2 and COS/O2) and their impact in the contact pattern transfer in the dielectric layers. In addition, this work was also dedicated to the understanding and limitation of metallic residues growth occurring after the contact etch process. This is carried out especially through the development of post etch plasma treatments.We performed XPS and EDX analyses to determine the mechanisms involved in the interactions between plasma processing steps and the masking materials (TiN, OPL). The plasma gas phase was also analyzed by Optical Emission Spectroscopy (OES).We show that the contact etch profile is influenced by the OPL etching process due to the interactions between the plasma and the TiN hard mask. These interactions may lead to a modification of the hard mask profile and are at the origin of the metallic contamination observed over the patterned wafer or the reactor walls. Due to this contamination, the contact profiles are deformed and the dielectric etch process may be stopped. Finally, we have shown that the state-of-art CH4-based post-etch-treatments introduced to limit the residues growth after dielectric patterning with a TiN mask can be improved by adding an oxygen-based reactor cleaning process before the post-treatment process.

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes.

Due to aggressive scaling in semiconductor industry, the traditional optical lithography system is facing great challenges printing 32nm and below circuit layouts. Various promising nanolithography techniques have been developed as alternative solutions for patterning sub-32nm feature size. This dissertation studies physical design related optimization problem for these emerging methodologies, mainly focusing on double patterning and electronic beam lithography. Double Patterning Lithography (DPL) decomposes a single layout into two masks, and patterns the chip in two exposure steps. As a benefit, the pitch size is doubled, which enhances the resolution. However, the decomposition process is not a trivial task. Conflict and stitch are its two main manufacturing challenges. First of all, a post-routing layout decomposer has been developed to perform simultaneous conflict and stitch minimization, making use of the integer linear programming and efficient graph reduction techniques. Compared to the previous work which optimizes conflict and stitch separately, the proposed method produces significantly better result. Redundant via insertion, another key yield improvement technique, may increase the complexity in DPL-compliance. It could easily introduce unmanufacturable conflict, while not carefully planned and inserted. Two algo- rithms have been developed to take care of this redundant via DPL-compliance problem in the design side. While design itself is not DPL-friendly, post-routing decomposition may not achieve satisfactory solution quality. An efficient framework of WISDOM has been further proposed to perform wire spreading for better conflict and stitch elimination. The solution quality has been improved in great extent, with a little extra layout perturbations. As another promising solution for sub-22nm, Electronic Beam Lithography (EBL) is a maskless technology which shoots desired patterns directly into a silicon wafer, with charged particle beam. EBL overcomes the diffraction limit of light in current optical lithography system, however, the low throughput becomes its key technical hurdle. The last work of my dissertation formulates and investigates a bin-packing problem for reducing the processing time of EBL. / text

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes.

En microélectronique, l'augmentation de la densité des composants est la solution principale pour améliorer la performance des circuits. Ainsi, la taille des structures définies par la lithographie diminue à chaque changement de nœud technologique. A partir du nœud 14 nm, la lithographie optique est confrontée à la limite de résolution pour les niveaux métalliques. Pour surmonter cet obstacle, les niveaux métalliques sont conçus en deux étapes successives de patterning regroupant chacune une étape de lithographie et une étape de gravure. Cette technique, nommée double patterning, requiert une métrologie adaptée car l'alignement entre les deux étapes et les dimensions critiques sont alors directement liées. La méthode de mesure développée dans cette thèse repose sur la scattérométrie et la mesure de l'alignement par diffraction. Un code de simulation a permis d'optimiser la conception des mires de mesure. De plus, la méthode de mesure adoptée a pu être validée expérimentalement. / In microelectronics, the increase of component density is the main solution to improve circuit performance. The size of the patterns defined by lithography is reduced at each change of technology node. From the 14 nm node, optical lithography is facing the resolution limit for metal levels. In order to overcome this hurdle, metal levels are designed in two successive steps of patterning, which is composed of lithography followed by etching. This double patterning technique requires an appropriate metrology since overlay between the two steps and critical dimensions are directly linked. The developed method is based on scatterometry and overlay measurement by diffraction. Using a simulation code, the measurement targets have been designed optimally. Then the adopted method has been validated experimentally.

As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration. / text

Optical lithography is an indispensible step in the process flow of Design for Manufacturability (DFM). Optical lithography simulation is a compute intensive task and simulation performance, or lack thereof can be a determining factor in time to market. Thus, the efficiency of lithography simulation is of paramount importance. Coherent decomposition is a popular simulation technique for aerial imaging simulation. In this thesis, we propose an approximate simulation technique based on the 2D wavelet transform and use a number of optimization methods to further improve polygon edge detection. Results show that the proposed method suffers from an average error of less than 6% when compared with the coherent decomposition method. The benefits of the proposed method are (i) > 20X increase in performance and more importantly (ii) it allows very large circuits to be simulated while some commercial tools are severely capacity limited and cannot even simulate a circuit as small as ISCAS-85 benchmark C17. Approximate simulation is quite attractive for layout optimization where it may be used in a loop and may even be acceptable for final layout verification.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed. / text