Three high performance circuits for a low power supply DRAM¡¦s are presented in this thesis. First, a modified multi-stage sense amplifier is proposed, that utilizes the auxiliary transmission gate and charge recycling technique. The auxiliary NMOS transistor of the multi-stage sense amplifier is replaced by the transmission gate to improve the sensing speed. In addition, the charge recycling technique is used to reduce the power dissipation of multi-stage sense amplifier. It improves the sensing time by 6.1ns (24.4%) compared to that of the conventional multi-stage sense amplifier and the power saving percentage of 25.6% compared to that of the conventional one. Second, an improved Standby Power Reduction (SPR) Circuit is reported. The capacitor boosting technique is utilized in our proposed Static Current Cut-off Standby Power Reduction (SCCSPR) Circuit, which turns off the always-on MOS transistor of SPR circuit. The power consumption is 30.9% reduced by our design compared to that of the conventional SPR circuit. Third, an improved voltage doubler is developed. The indirect switch is utilized in our proposed circuit, it provides larger gate source bias applied to the PMOS pass transistor. Thus, the current drivability is arisen and the pumping speed is improved as well. In the 2V supply voltage, the pumping speed of our modified voltage doubler is arisen about 18.6% compared to that of the conventional voltage doubler. These high performance circuits in this thesis are applied in a 1-Kbit DRAM circuits. A data access time of 36ns and total power consumption 52.58mW are attained when the supply voltage is 2V. The access time of 10.3ns (22.2%) and power consumption of 6.44mW (11%) are reduced compared to that of the conventional DRAM.

Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of each other while connected with a high-bandwidth and high-speed interconnect. In particular, die-stacking can be useful in boosting the effective bandwidth and speed of DRAM systems. Die-stacked DRAM caches have recently emerged as one of the top applications of die-stacking. They provide higher capacity than their SRAM counterparts and are faster than offchip DRAMs. In addition, DRAM caches can provide almost eight times the bandwidth of off-chip DRAMs. They, however, come with their own challenges. Since they are only twice as fast as main memory, they considerably increase latency for misses and incur significant energy overhead for remote lookups in snoop-based multi-socket systems. In this thesis, we present a Dual-Grain Filter for avoiding unnecessary accesses to the DRAM cache at reduced hardware cost and we compare it to recent works on die-stacked DRAM caches.

Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of each other while connected with a high-bandwidth and high-speed interconnect. In particular, die-stacking can be useful in boosting the effective bandwidth and speed of DRAM systems. Die-stacked DRAM caches have recently emerged as one of the top applications of die-stacking. They provide higher capacity than their SRAM counterparts and are faster than offchip DRAMs. In addition, DRAM caches can provide almost eight times the bandwidth of off-chip DRAMs. They, however, come with their own challenges. Since they are only twice as fast as main memory, they considerably increase latency for misses and incur significant energy overhead for remote lookups in snoop-based multi-socket systems. In this thesis, we present a Dual-Grain Filter for avoiding unnecessary accesses to the DRAM cache at reduced hardware cost and we compare it to recent works on die-stacked DRAM caches.

Thesis (Ph. D.)--University of Missouri-Columbia, 1999. / Typescript. Vita. Includes bibliographical references (leaves 276-280). Also available on the Internet.

Thesis (Ph. D.)--University of Missouri-Columbia, 1999. / Typescript. Vita. Includes bibliographical references (leaves 276-280). Also available on the Internet.

No description available.

The exploration of leveraging physical attributes of hardware for cryptographic purposes has become a topic of research. Among these avenues, the utilization of Physical Unclonable Functions (PUFs) is one feature that is widely studied. PUFs provide the ability to generate encryption keys for device authentication by exploiting inherent variations in physical structures. In this research work, the focus lies on probing the characteristics of a DRAM-based PUF structure on the Intel Galileo Platform to discern its degradation traits and assess its suitability as a cryptographic primitive. As the adoption of PUFs in diverse applications surges, it becomes imperative to scrutinize their susceptibility to various forms of side-channel attacks. The research work is divided into two parts. First, experimental investigations have been undertaken to ascertain the vulnerability of the DRAM PUF which is the magnetic fault injection to understand its resilience against such threats. Secondly, the analysis of PUF measurements has been conducted to elucidate its potential as a dependable source for physical cryptography, particularly in the context of the oblivious transfer protocol which is based on the fuzzy transfer protocol. The results contributes to a deeper understanding of its application as a physical token as well as the security implications associated with deploying PUFs in cryptographic applications and pave the way for the development of robust countermeasures to mitigate emerging risks. / Master of Science / In the digital realm of ubiquitous smart devices, ensuring security has become utmost important. Various studies have been conducted to explore the use of physical hardware features for cryptography. The PUF, which are characteristics of the hardware stemming from the variations in the manufacturing process is one such feature that can be used to generate a secure key for device verification. In this study, DRAM-based PUF structure is analyzed for two purposes. The first part of the research is the study of vulnerability of such DRAM-based PUF due to a type of external stimuli where magnetic field radiation is subjected on the DRAM cells to alter the original decay characteristics of the cells. It will help in providing an understanding of its risk towards such effects. The next part of the research work investigates the use of such DRAM-based PUF as a physical cryptographic key where the sender physically transfers the DRAM chip to the receiver and device authentication happens using the DRAM-based PUF. The research work aims to deepen the understanding of PUFs and their applications. This understanding is crucial for developing resilient security measures and address emerging threats posed by malicious attackers in the digital landscape. Ultimately, these efforts aim to ensure the integrity and confidentiality of sensitive information in an increasingly interconnected world.

記憶體是半導體產品之一，其規格及運用皆已標準化，沒有很大的差異性，價格受到供需的影響，因時因地而各不相同。由於，記憶體供應來源只局限少數幾家廠商，交易金額往往是百萬美元計，任何價格的變動都會影響企業營收，但是對記憶體模組業者而言，價格變動是常態，比其他的零組件波動性更強。在沒有進入障礙、價格波動、沒有龐大設廠資金及技術涉入下，記憶體模組業者，如何以更有效率的模式經營企業，以取得世界市場一席之地。 記憶體模組業者除了提供Memory Module外，現也經營Flash產品。這是因為Flash 產品的零件來源、組裝及通路與Memory Module有類似共通性，但Flash產品才崛起數年，而市場成長高於Memory Module，吸引許多非記憶體模組業者進入該市場，這其中包括國際性大廠，對現有的記憶體模組業者，如何以記憶體模組的經營模式，複製於Flash產品是另外一個課題。 本研究是探討記憶體模組業者，在記憶體模組及Flash 產品的經營模式，分別從其與供應商之關係、自有能力調整及與通路商之配合方式著手。此方式可以一窺記憶體模組業者，實際的經營方式與其他資訊硬體廠商大不相同，也構成外人無法知悉的進入障礙。 藉由廠商訪談，可以瞭解業者對記憶體模組及Flash產品運作的方式，最後本研究對記憶體模組業者提出二項建議：分別為面對變動環境下，應具備有的經營策略；如何強化自有的能力以面對未來的競爭。 / Memory, one of the semiconductor products, is a homogeneous product in terms of specification and application. Its prices are subject to the market - the supply and the demand at a certain time and place. The memory world is dominated by a limited number of makers, and one transaction usually amounts to millions of US dollars. A slight change in market price, therefore, would result in a noticeable number on the bottom line. However, to the memory module makers, price fluctuation is normal, though it is much more volatile than any other components. This study intends to explore how memory module makers can play a key role in the global market by getting more efficient under the premises that there are no entry barrier, price fluctuation, nor huge capital investment and high-tech involvement required. Memory modules players also carry flash products for these two products having similarity in their component source, assembly and marketing channel. The flash product, which appeared to the market just a few years ago, is a high-growth product and thus attractive to a herd of non-memory module makers, including international giants. How to apply the memory module business model to the flash product is a key subject for the existing memory module players. This study is aimed to discuss the business models used by memory module players to the memory modules and to the flash products. Relationship with suppliers, self adjustability and distributorship are separately explored herein. The finding is module players are actually running the business in a way greatly different from other hardware players and such difference in fact poses an entry barrier to the outsiders. Interviews with the industry players were conducted to gain insights to the business approaches being taken. At the end of this study, two suggestions are forwarded: the must-have business strategies in the ever-changing environment and the competitiveness for future challenges.

Les DRAMs sont des mémoires fréquemment utilisées dans les systèmes aéronautiques et spatiaux. Leur tenue aux radiations doit être connue pour satisfaire les exigences de fiabilité des applications critiques. Ces évaluations sont traditionnellement faites en accélérateur de particules. Cependant, les composants se complexifient avec l'intégration technologique. De nouveaux effets apparaissent, impliquant l'augmentation des temps et des coûts de test. Il existe une solution complémentaire, le laser impulsionnel, qui déclenche des effets similaires aux particules. Grâce à ces deux moyens de test, il s'est agi d'étudier les principaux modes de défaillance des DRAMs liés aux radiations : les SEUs (Single Event Upset) dans les plans mémoire, et les SEFIs (Single Event Functional Interrupt) dans les circuits périphériques. L'influence des motifs de test sur les sensibilités SEUs et SEFIs selon la technologie utilisée a ainsi été démontrée. L'étude a de plus identifié l'origine des SEFIs les plus fréquents. En outre, des techniques de test laser ont été développées pour quantifier les surfaces sensibles des différents effets. De ces travaux a pu être dégagée une nouvelle méthodologie de test destinée à l'industrie. Son objectif est d'optimiser l'efficacité et le coût des caractérisations, grâce à l'utilisation de l'outil laser de façon complémentaire aux accélérateurs de particules. Enfin, une nouvelle solution de tolérance aux fautes est proposée : basée sur la propriété des cellules DRAMs d'être immune aux radiations lorsqu'elles sont déchargées, cette technique permet la correction de tous les bits d'un mot logique. / DRAMs are frequently used in space and aeronautic systems. Their sensitivity to cosmic radiations have to be known in order to satisfy reliability requirements for critical applications. These evaluations are traditionally done with particle accelerators. However, devices become more complex with technology integration. Therefore new effects appear, inducing longer and more expensive tests. There is a complementary solution: the pulsed laser, which trigger similar effects as particles. Thanks to these two test tools, main DRAM radiation failure modes were studied: SEUs (Single Event Upset) in memory blocks, and SEFIs (Single Event Functional Interrupt) in peripheral circuits. This work demonstrates the influence of test patterns on SEU and SEFI sensitivities depending on technology used. In addition, this study identifies the origin of the most frequent type of SEFIs. Moreover, laser techniques were developed to quantify sensitive surfaces of the different effects. This work led to a new test methodology for industry, in order to optimize test cost and efficiency using both pulsed laser beams and particle accelerators. Finally, a new fault tolerant technique is proposed: based on DRAM cell radiation immunity when discharged, this technique allows to correct all bits of a logic word.

Scaling of electronic circuits from micro- to nanometer size determined the incredible development in computer technology in the last decades. In charge storage capacitors that are the largest components in dynamic random access memories (DRAM), dielectrics with higher permittivity (high-k) were needed to replace SiO2. Therefore ZrO2 has been introduced in the capacitor stack to allow sufficient capacitance in decreasing structure sizes. To improve the capacitance density per cell area, approaches with three dimensional structures were developed in device fabrication. To further enable scaling for future generations, significant efforts to replace ZrO2 as high-k dielectric have been undertaken since the 1990s. In calculations, CaTiO3 has been identified as a potential replacement to allow a significant capacitance improvement. This material exhibits a significantly higher permittivity and a sufficient band gap. The scope of this thesis is therefore the preparation and detailed physical and electrical characterization of ultrathin CaTiO3 layers. The complete capacitor stacks including CaTiO3 have been prepared under ultrahigh vacuum to minimize the influence of adsorbents or contaminants at the interfaces. Various electrodes are evaluated regarding temperature stability and chemical reactance to achieve crystalline CaTiO3. An optimal electrode was found to be a stack consisting of Pt on TiN. Physical experiments confirm the excellent band gap of 4.0-4.2 eV for ultrathin CaTiO3 layers. Growth studies to achieve crystalline CaTiO3 indicate a reduction of crystallization temperature from 640°C on SiO2 to 550°C on Pt. This reduction has been investigated in detail in transmission electron microscopy measurements, revealing a local and partial epitaxial growth of (111) CaTiO3 on top of (111) Pt surfaces. This preferential growth is beneficial to the electrical performance with an increased relative permittivity of 55 with the advantage of a low leakage current comparable to that in amorphous CaTiO3 layers. A detailed electrical analysis of capacitors with amorphous and crystalline CaTiO3 reveals a relative permittivity of 30 for amorphous and an excellent value of 105 for fully crystalline CaTiO3. The permittivity exhibits a quadratic dependence with applied electric field. Crystalline CaTiO3 shows a 1-3% drop in capacitance density and permittivity at a bias voltage of 1V, which is significantly lower compared to all results for SrTiO3 capacitors measured elsewhere. A capacitance equivalent thickness (CET) below 1.0 nm with current densities 1×10−8 A/cm2 have been achieved on carbon electrodes. Finally, CETs of about 0.5 nm with leakage currents of 1 × 10−7 A/cm2 on top of Pt/TiN fulfill the 2016 DRAM requirements following the ITRS road map of 2012. / Die Verkleinerung von elektronischen Bauelementen hin zu nanometerkleinen Strukturen beschreibt die unglaubliche Entwicklung der Computertechnologie in den letzten Jahrzehnten. In Ladungsspeicherkondensatoren, den größten Komponenten in Arbeitsspeichern, wurden dafür Dielektrika benötigt, die eine deutlich höhere Permittivität als SiO2 besitzen. ZrO2 wurde als geeignetes Dielektrikum eingeführt, um eine ausreichende Kapazität bei kleiner werdenen Strukturen sicherzustellen. Zur weiteren Verbesserung der Kapazitätsdichte pro Zellfläche konnten 3D Strukturen in die Chipherstellung integriert werden. Seit den 1990ern wurden parallel bedeutende Anstrengungen unternommen, um ZrO2 als Dielektrikum durch Materialien mit noch höherer Permittivität zu ersetzen. Nach Berechnungen stellt nun CaTiO3 eine mögliche Alternative dar, die eine weitere Verbesserung der Kapazität ermöglicht. Das Material besitzt eine deutlich höhere Permittivität und eine ausreichend große Bandlücke. Diese Arbeit beschäftigt sich deshalb mit Herstellung und detaillierter physikalischer und elektrischer Charakterisierung von extrem dünnen CaTiO3 Schichten. Zusätzlich wurden diverse Elektroden bezüglich ihrer Temperaturstabilität und der chemischen Stabilität untersucht, um kristallines CaTiO3 zu herhalten. Als eine optimale Elektrode stellte sich Pt auf TiN heraus. Physikalische Experimente an extrem dünnen CaTiO3 Schichten bestätigen die Bandlücke von 4,0-4,2 eV. Wachstumsuntersuchungen an kristallinem CaTiO3 zeigen eine Reduktion der Kristallisationstemperatur von 640°C auf SiO2 zu 550°C auf Pt. Diese Reduktion wurde detailliert mittels Transmissionselektronenmikroskopie untersucht. Es konnte für einige Schichten ein partielles lokales epitaktischesWachstum von (111) CaTiO3 auf (111) Pt gemessen werden. Dieses Vorzugswachstum ist vorteilhaft für die elektrischen Eigenschaften durch eine gesteigerte Permittivität von 55 bei gleichzeitig geringem Leckstrom vergleichbar zu amorphen Schichten. Eine genaue elektrische Analyse von Kondensatoren mit amorphen und kristallinem CaTiO3 ergibt eine Permittivität von 30 für amorphe und bis zu 105 für kristalline CaTiO3 Schichten. Die Permittivität zeigt eine quadratische Abhängigheit von der angelegten Spannung. Kristallines CaTiO3 zeigt einen 1-3% Abfall der Permittivität bei 1V, der wesentlich geringer ausfällt als vergleichbare Werte für SrTiO3. Eine zu SiO2 vergleichbare Schichtdicke (CET) von unter 1,0 nm mit Stromdichten von 1×10−8 A/cm2 wurde auf Kohlenstoffsubstraten erreicht. Mit Werten von 0,5 nm bei Leckstromdichten von 1×10−7 A/cm2 auf Pt/TiN Elektroden erfüllen die CaTiO3 Kondensatoren die Anforderungen der ITRS Strategiepläne für Arbeitsspeicher ab 2016.