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Validating DSP circuits modeled in VHDL involves generating test data, creating VHDL test benches, and simulating the test benches including models under test (MUTs). This is a laborious and time-consuming process. Therefore, it is desirable to develop a high level approach to automating and planning these tasks. This dissertation presents a high level test planning system for functional validation of VHDL DSP models. The system requirements parameterized from the specifications constitute the input space and serve as generics of test benches. Library-based test benches are developed using high level design tools. A test planning framework uses a goal tree structure as a vehicle of planning and documenting the testing activities. In a goal tree, test goals are given based on the specifications and test groups are defined to satisfy the test goals. Test groups partially constrain the system requirements and thus partition the input space into smaller and more manageable subspaces. A set of test strategies are then applied to the test groups for efficient test case design. Each test case is mapped to a configuration declaration of the test bench. The test bench is then simulated to generate test vectors against which the MUT is tested. The MUT response is compared with the gold response by a comparator and verdicts are reached by test oracles. An integrated test planning software system has been developed for test planning and test automation based on this approach. As an illustration of this approach, this dissertation uses the Synthetic Aperture Radar system as a case study. Completeness and effectiveness of the generated test set are evaluated. This dissertation also discusses approaches to hierarchical faulty module isolation for hierarchical circuits. Exposability is proposed to measure the extent that signal values are revealed to the tester and is used as the cost function for the faulty module search problem. An expanded goal tree which explores the functional and structural aspects of a hierarchical circuit is also presented. / Ph. D.

When bonds between copper and printed circuit board laminates are subjected to impulsive forces, the need arises to characterize fracture energies corresponding to related, high-speed failure events. Work (or energy) is required to create new surface area—with associated dissipation events—during fracture, and this energy (for a given material system) is dependent on the speed of crack propagation, the locus of failure, and the temperature of the bond when it is broken. Since the 90° peel test has been widely employed in quasi-static fracture testing of film adhesion for printed circuit board applications, this test was first used as a basis to which other test results could be compared. A test fixture was designed and built for quasi-static peel testing that accommodated peeling at different angles and temperatures. A similar test was then desirable for the direct comparison of dynamic fracture events to those quasi-static results. The “loop peel test” was thus developed to mimic the common 90° peel test and to quantify the time- and temperature-dependent fracture energies of peel specimens during low-velocity impact. This test has been successfully used to determine the apparent critical strain energy release rate of copper/epoxy bonds for low-velocity impact conditions (1-10 m/s), for a case of near-interfacial failure. The falling wedge test has also been adapted to estimate the apparent critical strain energy release rate at similar fracture conditions. Four types of printed circuit boards have been analyzed with the above impact test methods as well as with their corresponding quasi-static tests, and the fracture energies measured with the impact tests have been compared to those obtained using quasi-static tests. Fracture energies of the material systems considered were dependent on time (speed of fracture), temperature, and the amount of moisture migration, as determined via humidity conditioning parameters. / Master of Science

The purpose of this bachelor thesis was to evaluate the impact of uncertainty on test-enhanced learning. A within-groups experiment was designed to compare uncertainty under three study and retrieval conditions carried out in a single session; study-restudy-restudy, study-test-test with feedback and study-test-test without feedback. In this first session, 105 Swedish-Swahili word-pairs were presented to each participant. Participants then made judgments of learning on the word pairs. Subsequently, participants either re-studied the word-pair, were tested on the pair via cued recall and given feedback or tested without feedback. Participants were then tested in cued recall tests on the word pairs two hours and one week after the learning session, respectively. Ten participants were tested during three sessions which were administered on a web-based platform. The result indicate that no test-effect was found, and participants scored highest in the restudy condition at the cued recall tests. Judgment of learning score was a significant predictor of final cued recall scores on the final test. / I den här Kandidat uppsatsen görs ett försök att utvärdera hur känslan av osäkerhet att påverka test-effekten. Ett experiment designades för att utvärdera tre olika conditions, en studie-studie-studie, en studie-test-test med feedback och enstudie-test-test utan feedbacki en experimentell inom grupp design. Deltagarna ombads mellan delarna skatta sin skala av säkerhet på att kunna göra en framgångsrik återkallning efter en vecka. Allt deltagande var web baserat. Tio deltagare deltog i studien och de testades under tre olika tillfällen. Första tillfället med tre olika conditions, sedan med två uppföljande test tillfällen. Den första efter två timmar och ett avslutande test efter en vecka. Deltagarna testades på 105 ordpar Swahili-Svenska. Resultatet visar att ingen test-effekt uppnåddes och deltagarna nådde högst resultat på upprepad studie alternativet. Själv skattningen på deltagarnas skala av säkerhet var signifikant som indikator på korrekt återkallning efter en vecka i de två upprepad test delarna.

This study will pursue the inquiry in an attempt to add to the weight of evidence for or against the reliability of the Rorschach Test as an indicator of intelligence. The problem may be resolved into a comparison between various scoring categories or factors of the Rorschach and I.Q.

Test anxiety is a prevalent stressor which negatively impacts academic performance in evaluative situations. Previous literature has shown that attention biases (AB) to threats are implicated with general anxiety. However, few studies have examined the effect between AB to relevant threats (i.e., testing threats) and test anxiety. This study addressed previous gaps by examining whether temperamental effortful control and frontal EEG asymmetry (FA) impacted the relation between an exogenous AB to test threats and test anxiety in undergraduate students. A dot-probe task with test threat words as the target was given to the students. Paired-sample T tests show the presence of an AB to test threats in the endogenous (i.e., 500ms) condition but not in the exogenous (i.e., 250ms) condition. Hierarchical regression analyses showed that right FA modulated the positive relation between AB to test threats with test anxiety and positive relation between test anxiety with AB to test threats. Attentional control negatively predicted test anxiety but not the AB to test threats. AC and IC did not significantly interact with either test anxiety or AB to test threats in predicting the other (i.e., test anxiety predicting AB to test threats and vice-versa). A four-way interaction indicated that greater test anxiety predicts a stronger AB to test threats for those with right FA, low AC, and high IC. This four-way interaction result was conservatively considered due to the risk of overfitting. Results suggest the need to include FA in future studies of AB to test threats. / Doctor of Philosophy / Test anxiety is a prevalent stressor which negatively impacts academic performance in evaluative situations. Research shows that greater attention (i.e., attention biases; AB) to threats is related with general anxiety. However, few studies have examined the effect between AB to relevant threats (i.e., testing threats) and test anxiety. This study addressed previous gaps by examining whether temperamental effortful control and frontal EEG asymmetry (FA) impacted the relation between an exogenous AB to test threats and test anxiety in undergraduate students. A dot-probe task with test threat words as the target was given to the students. Paired-sample T tests show the presence of an AB to test threats in the endogenous (i.e., 500ms) condition but not in the exogenous (i.e., 250ms) condition. Results showed that positive relation between AB to test threats with test anxiety and positive relation between test anxiety with AB to test threats only occurred when students showed greater right FA. Lower attentional control predicted higher test anxiety but not the AB to test threats. AC and IC did not significantly interact with either test anxiety or AB to test threats in predicting the other (i.e., test anxiety predicting AB to test threats and vice-versa). A four-way interaction indicated that greater test anxiety predicts a stronger AB to test threats for those with right FA, low AC, and high IC. This four-way interaction result was conservatively considered due to the risk of overfitting. Results suggest the need to include FA in future studies of AB to test threats.

Test plans are used to guide, organize and document the testing activities during hardware design process. Manual test planning and configuration is known to be labor intensive, time consuming and error prone. It is desirable to develop efficient approaches to model testing and to develop test tools to automate test-planning activities. With the emergence of new hardware design paradigms, there is a need to develop more specialized description languages. However, adopting a new language for hardware-based designs involves adapting the existing design and verification tool suite for the new language. This is a very time consuming and capital intensive process. To ease the adoption of new description languages, it is desirable to develop multi-language support methodologies for design and test tools. This thesis addresses a subset of these problems. It presents a goal-tree based test methodology which is very effective for functional testing of hardware models in multiple application domains. Then it describes an approach for achieving a high degree of language independence using ideas of data abstraction. It also presents an automated test-planning tool called the "Goal Tree System (GTS)", which provides an implementation of goal tree methodology and multi-language support ideas. We demonstrate the use of this tool by testing models developed in VHDL and SystemC. We also present the design aspects of the Goal Tree System, which enable it to work across multiple platforms and with multiple simulators. / Master of Science

Yes / The difference between Apolipoprotein E ε4 carriers and non-carriers in response to single exercise sessions was tested. Stroop and Posner tasks were administered to young untrained women immediately after walking sessions or moderately heavy exercise. Exercise had a significantly more profound impact on the Stroop effect than on the Posner effect, suggesting selective involvement of prefrontal function. A significant genotype-by-exercise interaction indicated differences in response to exercise between ε4 carriers and non-carriers. Carriers showed facilitation triggered by exercise. The transient executive down-regulation was construed as due to exercise-dependent hypofrontality. The facilitation observed in carriers was interpreted as better management of prefrontal metabolic resources, and explained within the antagonistic pleiotropy hypothesis framework. The findings have implications for the interpretation of differences between ε4 carriers and non-carriers in the benefits triggered by long-term exercise that might depend, at least partially, on mechanisms of metabolic response to physical activity. / Partially supported by a University of Hull Faculty of Science scholarship to MDM and by funding from MIUR and FP7 VPH-DARE to AV.

Integrated circuits, from general purpose microprocessors to application specific designs (ASICs), have become ubiquitous in modern technology. As our applications have become more complex, so too have the circuits used to drive them. Moore's law predicts that the number of transistors on a chip doubles every 18-24 months. This explosion in circuit size has also lead to significant growth in testing effort required to verify the design. In order to cope with the required effort, the testing problem must be approached from several different design levels. In particular, exploiting the Register Transfer Level for test generation allows for the use of relational information unavailable at the structural level. This dissertation demonstrates several novel methods for generating tests applicable for both structural and functional tests. These testing methods allow for significantly faster test generation for functional tests as well as providing high levels of fault coverage during structural test, typically outperforming previous state of the art methods. First, a semi-formal method for functional verification is presented. The approach utilizes a SMT-based bounded model checker in combination with an ant colony optimization based search engine to generate tests with high branch coverage. Additionally, the method is utilized to identify unreachable code paths within the RTL. Compared to previous methods, the experimental results show increased levels of coverage and improved performance. Then, an ant colony optimization algorithm is used to generate high quality tests for fault coverage. By utilizing co-simulation at the RTL and gate level, tests are generated for both levels simultaneously. This method is shown to reach previously unseen levels of fault coverage with significantly lower computational effort. Additionally, the engine was also shown to be effective for behavioral level test generation. Next, an abstraction method for functional test generation is presented utilizing program slicing and data mining. The abstraction allows us to generate high quality test vectors that navigate extremely narrow paths in the state space. The method reaches previously unseen levels of coverage and is able to justify very difficult to reach control states within the circuit. Then, a new method of fault grading test vectors is introduced based on the concept of operator coverage. Operator coverage measures the behavioral coverage in each synthesizable statement in the RTL by creating a set of coverage points for each arithmetic and logical operator. The metric shows a strong relationship with fault coverage for coverage forecasting and vector comparison. Additionally, it provides significant reductions in computation time compared to other vector grading methods. Finally, the prior metric is utilized for creating a framework of automatic test pattern generation for defect coverage at the RTL. This framework provides the unique ability to automatically generate high quality test vectors for functional and defect level testing at the RTL without the need for synthesis. In summary, We present a set of tools for the analysis and test of circuits at the RTL. By leveraging information available at HDL, we can generate tests to exercise particular properties that are extremely difficult to extract at the gate level. / Ph. D. / Digital circuits and modern microprocessors are pervasive in modern life. The complexity and scope of these devices has dramatically increased to meet new demands and applications, from entertainment devices to advanced automotive applications. Rising complexity causes design errors and manufacturing defects are more difficult to detect and increases testing costs. To cope with rising test costs, significant effort has been directed towards automating test generation early in development when defects are less expensive to correct. Modern digital circuits are designed using Hardware Description Languages (HDL) to describe their behavior at a high logical level. Then, the behavioral description is translated to a chip level implementation. Most automated test tools use the implementation description since it is a more direct representation of the manufactured circuit. This dissertation demonstrates several methods to utilize available logical information in behavioral descriptions for generating tests early in development that maintain applicability throughout the design process. The proposed algorithms utilize a biologically-inspired search, the ant colony optimization, abstracting test generation as an ant colony hunting for food. In the abstraction, a sequence of inputs to a circuit is represented by the walked path of an individual ant and untested portions of the circuit description are modelled as food sources. The final test is a collection of paths that efficiently reach the most food sources. Each algorithm also explores different software analysis techniques, which have been adapted to handle unique constraints of HDLs, to learn about the target circuits. The ant colony optimization uses the analysis to help guide and direct the search, yielding more efficient execution than prior techniques and reducing the time required for test generation. Additionally, the described methods can automatically generate tests in cases previously requiring manual generation, improving overall test quality.

No / The medial temporal lobe (MTL) memory system is damaged early in Alzheimer's disease. Cognitive tests designed to help diagnose the disease must detect dysfunction in this system, but must also be insensitive to the cognitive slowing that characterizes normal ageing. On the assumption that the MTL system forms new memories by binding together the many informational aspects of events into units, The Placing Test was designed to index this function by measuring the ability to remember associations between faces and their locations. The influence of normal ageing was minimized by using procedures that compensate for the difficulties in learning and retrieval caused by the cognitive slowing of normal ageing. In two experiments The Placing Test was administered as part of a battery of neuropsychological tests to a group of healthy older people. In both studies, performance in The Placing Test correlated significantly with other measures of memory, but had weaker associations than standard memory measures with other types of cognitive function. The Placing Test appeared not to be biased by age, education or gender, although a larger sample is needed to verify this. A final study examined the performance of 16 patients with suspected Alzheimer's disease. These patients showed clear impairment in The Placing Test, with 81% scoring below the 5th percentile, despite the majority having normal MMSE scores. It is concluded that The Placing Test provides a quick, simple and sensitive measure of memory that has potential to be useful in routine diagnostic investigations for Alzheimer's disease.