Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.

Ethernet är den standard som används nästan överallt för nätverk i hemmen, på kontor och i industrier. Varken Ethernet eller switchat Ethernet är gjorda för att hantera realtidskommunikation då tiden det tar att skicka ett meddelande inte alltid sker inom en förutsägbar tid. I denna rapport presenteras ett protokoll som tillåter feltolerant dynamisk schemaläggning av kanaler över ett switchat Ethernet. Protokollet är en vidareutveckling av tidigare arbete (ThrottleNet) som gjorts inom området där realtidstrafik ska garanteras över ett switchat Ethernet. Till skillnad från tidigare arbete använder sig detta protokoll av kritikaliteter för att explicit visa skillnaden mellan de kanaler som får tas bort och de kanaler som inte får tas bort. Kanalerna schemaläggs vid kortvariga överbelastningar för att optimera användningen av tillgängliga resurser baserat på hur värdefulla och kritiska kanalerna är för systemet.

Ethernet functionality testing as a generic term used for checking connectivity,throughput and capability to transfer packets over the network. Especially in the packet-switchenvironment, Ethernet testing has become an essential part for deploying a reliable network.Over a long distance Ethernet testing parameter for analyzing network performance must havetwo devices attached and synchronized. Saab Microwave Systems is among the leading suppliers of radar systems developing groundbased,naval and air-borne radar systems. To ensure the correct functionality, the developerwants to verify the performance of computer network and looking for a suitable solution. A software application is required to verify and test the functionality of the Ethernet network andto verify the functionality and performance of the TCP/IP stack of newly added node. Theprograms shall be easily ported to different operating systems and must not depend on specificproduct properties.A software application, “NetBurst”, is developed for Ethernet functionality testing. Theapplication is vendor and platform independent.

In the industry there is a need for a more efficient way to troubleshoot machines that uses the protocol EtherNet/IP. The current methods is time consuming and complex. This project gather data from a simulated network and analyze the data. The result of the analyze is presented on a cellphone application with a description and a possible solution. The application is a cross-platform application developed with Cordova. The simulated network is created on a Raspberry Pi 2. The analyze is done on another Raspberry Pi 2 running the software Node-RED. Communication between the simulated network Raspberry and the cellphone is with Bluetooth Low Energy. Communication between cellphone and the server is with MQTT. There are several areas where this kind of application may suit. This project is in one specific area – troubleshooting EtherNet/IP.

Ingeniero Civil Eléctrico / Uno de los protocolos de la capa de transporte más importantes, Transport Control Protocol (TCP), garantiza que los paquetes sean recibidos en forma ordenada e integra y aborda el problema de la congestión evitando transmitir paquetes nuevos si el receptor no ha notificado que los paquetes enviados con anterioridad han sido recibidos. Se observa en su comportamiento, por una parte, que la velocidad de transmisión de datos es afectada negativamente respecto a la distancia entre el transmisor y receptor. Por otra parte para evitar la congestión el protocolo solo detecta la existencia de tráfico, sin la capacidad de estimar su magnitud. Con el fin de abarcar las debilidades de TCP, en relación al efecto provocado por la distancia entre transmisor y receptor, la eficiencia de la transmisión y el problema de la congestión de tráfico, el Dr. Claudio Estévez ha desarrollado la teoría de un protocolo de transporte orientado a redes Carrier Ethernet, que mejora la eficiencia de la capa de transporte, llamado ESTP (Ethernet-Services Transport Protocol). Para llevar a la realidad la propuesta recién descrita, surge el problema de investigación de esta memoria: ¿La implementación de ESTP valida el modelo teórico presentando un mejorcomportamiento que los métodos de congestión tradicionales? . Así, el propósito de esta memoria es concretar la codificación de un modulo de congestión en Linux para implementar ESTP y posteriormente compararlo con la teoría planteada por el Dr. Claudio Estévez y con otros protocolos existentes, particularmente BIC, CUBIC y RENO. Los principales resultados de este trabajo caracterizan el comportamiento experimental de ESTP comparándolo con la teoría en que se basa la implementación, en cuanto al comportamiento en el tiempo y a variaciones de Round Trip Time (RTT), poniendo énfasis en la reducción de la ventana de congestión, el cumplimiento de las condiciones de Carrier-Ethernet y la reducción del cuello de botella impuesto por la capa de transporte para valores altos de RTT. Además los resultados experimentales se contrastan con el funcionamiento general de otros métodos de congestión bajo un ambiente de pruebas controlado, demostrando la superioridad de ESTP en la medida que los valores de RTT aumentan. Así, se observa que a un valor de RTT de 70[ms], en un ambiente de pérdida variable, el flujo de datos de ESTP es superior a BIC en un 35,7% , a CUBIC en un 41,1% y a RENO en un 71,8%. Cabe señalar que a raíz de esta investigación se publicaron tres papers titulados: A Carrier-Ethernet Oriented Transport Protocol with a Novel Congestion Control and QoS Integration: Analytical, Simulated and Experimental Validation ( ICC 2012), Ethernet-Services Transport Protocol Design oriented to Carrier Ethernet Networks (GLOBECOM 2012) y Ethernet-Services Transport Protocol forCarrier Ethernet Networks ( ICCCN 2012). Además de un journal enviado, denominado: QoS-supporting Transport Protocol with Congestion Intensity Estimation .

M.Ing. / Recent traffic analyses have shown the existence of long-range dependencies in network traffic, specifically self-similar long-range dependencies. Due to the inability of traditional traffic models to capture these long-range dependencies, new network traffic models were developed that are able to capture it. In this paper we compare three self-similar long-range dependent traffic models, namely the FARIMA model, the wavelet independent Gaussian model and the multifractal wavelet model. We present results on their marginal distributions, their correlation matching to real traffic and their queuing behaviour. We show that the multifractal wavelet model is the best of the three models in all of the test aspects.

This paper describes the basic concepts of our solution to improve the performance of Ethernet Communication on a Linux Cluster environment by introducing Reliable Low Latency Ethernet Sockets. We show that about 25% of the socket latency can be saved by using our simplified protocol. Especially, we put emphasis on demonstrating that this performance benefit is able to speed up the MPI level communication. Therefore we have developed a new BTL component for Open MPI, an open source MPI-2 implementation which offers with its Modular Component Architecture a nearly ideal environment to implement our changes. Microbenchmarks of MPI collective and Point-to-Point operations were performed. We see a performance improvement of 8% to 16% for LU and SP implementations of the NAS parallel benchmark suite which spends a significant amount of time in the MPI. Practical application tests with Abinit, an electronic structure calculation program, show that the runtime of be nearly halved on a 4 node system. Thus we show evidence that our new Ethernet communication protocol is able to increase the speedup of parallel applications considerably.

Audio Engineers are required to design and deploy large multi-channel sound systems which meet a set of requirements and use networking technologies such as Firewire and Ethernet AVB. Bandwidth utilisation and parameter groupings are among the factors which need to be considered in these designs. An implementation of an extensible, generic simulation framework would allow audio engineers to easily compare protocols and networking technologies and get near real time responses with regards to bandwidth utilisation. Our hypothesis is that an application-level capability can be developed which uses a network simulation framework to enable this process and enhances the audio engineer’s experience of designing and configuring a network. This thesis presents a new, extensible simulation framework which can be utilised to simulate professional audio networks. This framework is utilised to develop an application - AudioNetSim - based on the requirements of an audio engineer. The thesis describes the AudioNetSim models and implementations for Ethernet AVB, Firewire and the AES- 64 control protocol. AudioNetSim enables bandwidth usage determination for any network configuration and connection scenario and is used to compare Firewire and Ethernet AVB bandwidth utilisation. It also applies graph theory to the circular join problem and provides a solution to detect circular joins.

Knowledge of a network’s entities and the physical connections between them, a network’s physical topology, can be useful in a variety of network scenarios and applications. Administrators can use topology information for fault- finding, inventorying and network planning. Topology information can also be used during protocol and routing algorithm development, for performance prediction and as a basis for accurate network simulations. Specifically, from a network security perspective, threat detection, network monitoring, network access control and forensic investigations can benefit from accurate network topology information. The dynamic nature of large networks has led to the development of various automatic topology discovery techniques, but these techniques have mainly focused on cooperative network environments where network elements can be queried for topology related information. The primary objective of this study is to develop techniques for discovering the physical topology of an Ethernet network without the assistance of the network’s elements. This dissertation describes the experiments performed and the techniques developed in order to identify network nodes and the connections between these nodes. The product of the investigation was the formulation of an algorithm and heuristic that, in combination with measurement techniques, can be used for inferring the physical topology of a target network. / Dissertation (MSc)--University of Pretoria, 2008. / Computer Science / unrestricted