The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

Gallium Nitride (GaN) and its alloys with InN and AlN, the III-nitrides, are of interest for a variety of high power-high frequency electronics and optoelectronics applications. However, unlike Si and GaAs technology that have been developed on native substrates, III-nitride devices have been developed on non-native substrates such as Si, sapphire and SiC. This is because bulk cheap native III-nitride substrates are unavailable. Among the known substrates, III-nitride technology development on Si is desirable because of its large substrate size and low cost. However, the large lattice and thermal expansion mismatch between the III-nitrides films and Si substrate leads to a high level of dislocations, 1010 cm-2, and tensile stress which results in cracking. For successful integration of crack free and low dislocation density GaN on Si various kinds of transition layer schemes are used that help to incorporate a compressive growth stress to neutralize the tensile thermal mismatch stresses and also to reduce dislocation densities to levels required by devices. These transition schemes, ranging from 400 nm to 7 m, involve the use of graded AlGaN layers, high/low temperature interlayers and superlattices. The aim of the research described in this thesis was a systematic comparison of the different transition layer schemes currently used with the objective of increasing the efficiency of integrating device quality, crack free, low dislocation density, <109 cm-2, GaN with Si. A metal organic chemical vapor deposition equipped with an in-situ stress monitor was used for growth. Transmission electron microscopy was used for quantitative measurement of dislocation density. The research shows, for the first time, that all transition layer optimization depends critically on the Si surface made available for growth of the first AlN layer. It needs to be optimally cleaned such that it is oxide free and smooth. A quantitative TEM comparison of various currently used transition layer schemes shows that while they have interesting mechanistic differences, they are not very different in their dislocation reduction efficiency. All of them yield a final dislocation density in a probe GaN layer of 1-3×109 cm-2. In contrast, a combination of Si doping and compressive growth stress has a synergistic effect on dislocation reduction. A simple 210 nm transition layer based on this understanding, the lowest reported yet, yields GaN layers that are crack free and have lower <1x109 cm-2 dislocation density, than those obtained by the aforementioned more complicated schemes. High electron mobility transistor characteristics performance on the probe GaN layers obtained on these transition layers supports the structural observations above.

Les matériaux III-N sont présents dans la vie quotidienne pour des applications optoélectroniques (diodes électroluminescentes, lasers). Les propriétés remarquables du GaN (grand gap, grand champ de claquage, champ de polarisation élevé, vitesse de saturation des électrons importante…) en font un candidat de choix pour des applications en électronique de puissance à basse fréquence, mais aussi à haute fréquence, par exemple en gamme d'ondes millimétriques. L’enjeu de ce travail de thèse consiste à augmenter la fréquence de travail des transistors tout en maintenant une puissance élevée. Pour cela, des hétérostructures HEMTs (High Electron Mobility Transistors) sont développées et les épaisseurs de cap et de barrière doivent être réduites, bien que ceci soit au détriment de la puissance délivrée. Une étude sera donc menée sur l’influence des épaisseurs de cap et de barrière ainsi que le type de barrière (AlGaN, AlN et InAlN) de manière à isoler les hétérostructures offrant le meilleur compromis en termes de fréquence et de puissance. De plus, les moyens mis en œuvre pour augmenter la fréquence de travail entrainent une dégradation du confinement des électrons du canal. De manière à limiter cet effet, une back-barrière est insérée sous le canal. Ceci fera l’objet d’une deuxième étude. Enfin, une étude de la passivation de surface des transistors sera menée. La combinaison des ces trois études permettra d’identifier la structure optimale pour délivrer le plus de puissance à haute fréquence (ici à 40 GHz). / Nitride based materials are present in everyday life for optoelectronic applications (light emitting diodes, lasers). GaN remarkable properties (like large energy band gap, high breakdown electric field, high polarization field, high electronic saturation velocity…) make it a promising candidate for low frequency power electronic applications, but also for high frequency like microwaves range for example. The aim of this work is to increase the transistors working frequency by keeping a high power. To do this, high electron mobility transistor heterostructures are developed, and cap and barrier thicknesses have to be reduced, although it is detrimental for a high power. A first study deals with the influence of cap and barrier thicknesses as well as the type of barrier (AlGaN, AlN and InAlN), in order to isolate heterostructures offering the best compromise in terms of power and frequency. Moreover, the means implemented to increase the working frequency lead to electron channel confinement degradation. In order limit this effect, a back-barrier is added underneath the channel. It will be the subject of the second study. Finally, a transistor surface passivation study will be led. The combination of those three parts will allow identifying the optimum structure to deliver the highest power at high frequency (here at 40 GHz).

Heterostructures of the materials system GaN/AlGaN/GaN were grown by molecular beam epitaxy on 6H-SiC substrates and high electron mobility transistors (HEMTs) were fabricated. For devices with large gate periphery an air bridge technology was developed for the drain contacts of the finger structure. The devices showed DC drain currents of more than 1 A/mm and values of the transconductance between 120 and 140 mS/mm. A power added efficiency of 41 % was measured on devices with a gate length of 1 µm at 2 GHz and 45 V drain bias. Power values of 8 W/mm were obtained. Devices with submicron gates exhibited power values of 6.1 W/mm (7 GHz) and 3.16 W/mm (25 GHz) respectively. The rf dispersion of the drain current is very low, although the devices were not passivated. / Heterostrukturen im Materialsystem GaN/AlGaN/GaN wurden mittels Molekularstrahlepitaxie auf 6H-SiC-Substraten gewachsen und High-Electron-Mobility-Transistoren (HEMTs) daraus hergestellt. Für Bauelemente mit großer Gateperipherie wurde eine Air-Bridge-Technik entwickelt, um die Drainkontakte der Fingerstruktur zu verbinden. Die Bauelemente zeigten Drainströme von mehr als 1 A/mm und Steilheiten zwischen 120 und 140 mS/mm. An Transistoren mit Gatelängen von 1 µm konnten Leistungswirkungsgrade (Power Added Efficiency) von 41 % (bei 2 GHz und 45 V Drain-Source-Spannung) sowie eine Leistung von 8 W/mm erzielt werden. Bauelemente mit Gatelängen im Submikrometerbereich zeigten Leistungswerte von 6,1 W/mm (7 GHz) bzw. 3,16 W/mm (25 GHz). Die Drainstromdispersion ist sehr gering, obwohl die Bauelemente nicht passiviert wurden.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are favored for their smaller specific on-resistance, lower switching losses, and higher theoretical temperature limits as compared to traditional silicon (Si) power switches. They have the potential to dramatically increase the power density and efficiency of power electronics systems by replacing traditional Si-based switches. However, GaN HEMTs have a faster switching speed compared to their Si-based counterparts. Minimizing the parasitic loop inductances of the GaN HEMT package is crucial for reducing electromagnetic interference (EMI) noise and voltage spikes. Another concern with GaN HEMTs comes from their lower thermal conductivity and smaller die size. The HEMTs generally have a higher heat flux density, and accordingly, demand better heat dissipation. Thus, innovations are needed for making GaN HEMT packages with low parasitic inductances and higher thermal performances to further their applications in high-frequency, high-power-density converters. To reduce loop inductance, other researchers have embedded GaN HEMTs in a printed circuit board (PCB) and used plated vias for interconnections and heat dissipation. However, this approach requires more complex manufacturing steps and has lower thermal performance. This dissertation introduces different embedded packaging techniques for 650V, 150A GaN HEMTs; this method involves interconnecting the bare chips between direct-bonded copper (DBC) and a PCB or between two DBCs, as discussed in Chapter 2. Vertical interconnections by gold pins and silver rods are introduced and implemented in embedded packages to limit the parasitic loop inductance within 1.5 nH and parasitic resistances within 1.5 mΩ. The thermal performance of the embedded GaN HEMT packages is experimentally verified in Chapter 2; then, the junction-to-case thermal resistance (RthJC) measurement is discussed in Chapter 3. The common temperature-sensitive electrical parameters (TSEPs) of a GaN HEMT for junction temperature measurement lack sufficient sensitivity or stability due to the electron-trapping effect. The non-uniform distribution of the case temperature and a large temperature gradient between the case and heatsink also make it difficult to accurately measure the case temperature. In Chapter 3, gate-to-gate resistance (Rg2g) is selected as the TSEP for junction temperature measurement. The stacked thermal interface material (TIM) technique was used to reduce errors in case temperature measurement. This technique was implemented in a custom GaN HEMT package and in embedded GaN HEMT packages for measuring junction-to-case thermal resistance. The discrepancy between measurement and simulation is less than 20%, and the junction-to-case thermal resistance for embedded packages is within 0.1 °C/W. Chapter 4 evaluates the reliability of the GaN HEMT embedded packages developed in Chapter 2 by utilizing a power cycling test. Monitoring the junction temperature of the embedded packages online is challenging during the power cycling test. Other approaches have used the on-resistance as the TSEP in order to monitor junction temperature for GaN HEMTs but this is not accurate due to electron trapping. As discussed in Chapter 3, Rg2g is chosen as the TSEP to monitor the junction temperature without worrying about the influence of electron trapping, and this approach cycles the embedded packages at 75 A from 25°C to 125°C. The packages can endure 23,000 power cycles before failure. This work is the first to develop, fabricate, and characterize embedded packages for 650V, 150A GaN HEMT bare chips. These embedded packages with high-power-rated GaN HEMT bare dice provide an opportunity to reduce the number of paralleled power switches, reduce the system's cooling size, and increase the system's power density. In addition, this work is the first to develop the junction-to-case thermal resistance measurement technique by gate-to-gate electrical resistance and stacked-TIM for GaN HEMT packages. The technique helps enable solid thermal design for power electronics systems. / Doctor of Philosophy / Power switches are everywhere in our daily life. They are the fundamental elements in power converters for converting power to electric vehicles. As global power demand for these applications continues to increase, high levels of both efficiency and power density are crucial for power switches. However, traditional silicon-based switches are already very mature, and their properties are very close to their theoretical limits. For further improvement, researchers have tried to replace traditional Si switches with wide-bandgap switches, which have much higher theoretical limits. Gallium nitride high-electron-mobility transistors (GaN HEMTs) are one of the candidates. However, packaging these switches (GaN HEMTs) is challenging due to their initial properties. They naturally switch very quickly and have smaller sizes compared to traditional Si-based switches. The fast switching speed brings high dv/dt and di/dt during the switching period. It causes voltage spikes and electromagnetic interference (EMI) issues. And the smaller size contributes to higher heat flux density, thus requiring more efficient heat dissipation. To solve the challenge of packaging GaN HEMTs, this dissertation has developed embedded packaging techniques to achieve quiet switching and good heat dissipation. These packaging techniques enable GaN HEMTs' advantages and increase the power density and efficiency of power electronics systems. To experimentally verify the thermal performance of the embedded packages developed a junction-to-case thermal resistance measurement technique was introduced. The thermal resistance of a custom GaN HEMT package was measured, as were those of the embedded packages CPES also developed. The simulation results and the experimental results are close to each other. Finally, to further evaluate whether or not the newly developed embedded packages are reliable, power cycling tests were carried out at I = 75 A. The packages survived over 23,000 cycles before failure.

GaN-HEMTs (Gallium Nitride-based High Electron Mobility Transistors) have, thanks to the large band gap of GaN, electrical properties that are suitable for applications of high electrical voltages, high currents, and fast switching. The large band gap also gives GaN-HEMTs a high resistance to radiation. In this degree project, the effects of 2 MeV proton irradiation of GaN-HEMTs constructed on both silicon carbide and silicon substrates are investigated. 20 transistors per substrate were irradiated in the particle accelerator 5 MV NEC Pelletron in the Ångström laboratory at Uppsala University. These transistors were exposed to radiation doses in the range of 10^11 to 10^15 protons/cm^2. The analysis shows that both transistors on silicon, as well as silicon carbide, are unaffected by proton irradiation up to a dose of 10^14 protons/cm^2. GaN-on-Si transistors show less influence of radiation than GaN-on-SiC transistors. The capacitances between gate and drain as well as drain and source for both GaN-on-SiC and GaN-on-Si HEMTs show hysteresis as a function of forward and backward gate voltage sweeps for the radiation dose of 10^15 protons/cm^2. / GaN-HEMTs (Galliumnitridbaserade High Electron Mobility Transistors) har tack vare det stora bandgapet i GaN goda elektriska egenskaper som lämpar sig för höga elektriska spänningar, höga strömmar och snabb växling mellan av- och på-tillstånd. Det stora bandgapet ger även GaN-HEMTs ett stort motstånd mot strålning.I detta examensarbete undersöks effekterna av 2 MeV protonbestrålning av GaN-HEMTs. Dessa HEMTs är konstruerade på både kiselkarbid- och kiselsubstrat.20 transistorer per transistorsubstrat bestrålades i partikelacceleratorn 5 MV NEC Pelletron i Ångströmslaboratoriet vid Uppsala Universitet. Dessa transistorer utsattes för strålningsdoser inom intervallet 10^11 till 10^15 protoner/cm^2. Resultaten visar att både tranisistorer på kisel såsom kiselkarbid är opåverkade av strålning upp till en dos av 10^14 protoner/cm^2. GaN-på-Si-transistorer visar en mindre påverkan av protonstrålning än GaN-på-SiC-transistorer. Ytterligare uppstod hysteresis för kapacitanser mellan gate och drain och mellan gate och source som en funktion av fram- och bakriktad gate-spänning efter en strålningsdos av 10^15 protoner/cm^2.

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Le projet industriel français MEGaN vise le développement de module de puissance à base de compostant HEMT en GaN. Une des application industrielle concerne l’aéronautique avec une forte contrainte en isolation galvanique (>100 kV/s) et en température ambiante (200°C). Le travail de thèse a été concentré sur une brique module de puissance (bras d’onduleur 650 V 30 A). L’objectif est d’atteindre un prototype de facteur de forme peu épais, 30 cm2 et embarquant l’ensemble des fonctions driver, alimentation de driver, la capacité de bus et capteur de courant phase. Cet objectif implique un fort rendement énergétique, et le respect de l’isolation galvanique alors que la contrainte en surface est forte. Le manuscrit, outre l’état de l’art relatif au module de puissance et notamment celui à base de transistor GaN HEMT, aborde une solution d’isolation de signaux de commande à base de micro-transformateur. Des prototypes de micro-transformateur ont été caractérisés et vieillis pendant 3000 H pour évaluer la robustesse de la solution. Les travaux ont contribué à la caractérisation de plusieurs composants GaN afin de mûrir des modèles pour la simulation circuit de topologie de convertisseur. Au sein du travail collaboratif MEGaN, notre contribution ne concernait pas la conception du circuit intégré (driver de grille), tout en ayant participé à la validation des spécifications, mais une stratégie d’alimentation du driver de grille. Une première proposition d’alimentation isolée pour le driver de grille a privilégié l’utilisation de composants GaN basse-tension. La topologie Flyback résonante avec clamp permet de tirer le meilleur parti de ces composants GaN mais pose la contrainte du transformateur de puissance. Plusieurs technologies pour la réalisation du transformateur ont été validées expérimentalement et notamment une proposition originale enfouissement du composant magnétique au sein d’un substrat polymère haute-température. En particulier, un procédé de fabrication peu onéreux permet d’obtenir un dispositif fiable (1000 H de cyclage entre - 55 ; + 200°C), avec un rendement intrinsèque de 88 % pour 2 W transférés. La capacité parasite d’isolation est réduite par rapport aux prototypes précédent. Deux prototypes d’alimentations à forte intégration utilisent soit les transistors GaN basse tension (2.4 MHz, 2 W, 74 %, 6 cm2), soit un circuit intégré dédié en technologie CMOS SOI, conçu pour l’application (1.2 MHz, 2 W, 77 %, 8.5 cm2). Le manuscrit propose par la suite une solution intégrable de mesure de courant de phase du bras de pont, basé sur une magnétorésistance. La comparaison expérimentale vis à vis d’une solution à résistance de shunt. Enfin, deux prototypes de convertisseur sont décrits, dont une a pu faire l’objet d’une validation expérimentale démontrant des pertes en commutation réduites. / The french industrial project MEGaN targets the development of power module based on GaN HEMT transistors. One of the industrial applications is the aeronautics field with a high-constraint on the galvanic isolation (>100 kV/s) and ambient temperature (200°C). The intent of this work is the power module block (3 phases inverter 650 V 30 A). The goal is to obtain a small footprint module, 30 cm2, with necessary functions such as gate driver, gate driver power supply, bulk capacitor and current phase sensor. This goal implies high efficiency as well as respect of the constraint of galvanic isolation with an optimized volume. This dissertation, besides the state of the art of power modules and especially the GaN HEMT ones, addressed a control signal isolation solution based on coreless transformers. Different prototypes based on coreless transformers were characterized and verified over 3000 hours in order to evaluate their robustness. The different studies realized the characterization of the different market available GaN HEMTs in order to mature a circuit simulation model for various converter topologies. In the collaborative work of the project, our contribution did not focus on the gate driver chip design even if experimental evaluation work was made, but a gate driver power supply strategy. The first gate driver isolated power supply design proposition focused on the low-voltage GaN HEMT conversion. The active-clamp Flyback topology allows to have the best trade-off between the GaN transistors and the isolation constraint of the transformer. Different transformer topolgies were experimentally performed and a novel PCB embedded transformer process was proposed with high-temperature capability. A lamination process was proposed for its cost-efficiency and for the reliability of the prototype (1000 H cycling test between - 55; + 200°C), with 88 % intrinsic efficiency. However, the transformer isolation capacitance was drastically reduced compared to the previous prototypes. 2 high-integrated gate driver power supply prototypes were designed with: GaN transistors (2.4 MHz, 2 W, 74 %, 6 cm2), and with a CMOS SOI dedicated chip (1.2 MHz, 2 W, 77 %, 8.5 cm2). In the last chapter, this dissertation presents an easily integrated solution for a phase current sensor based on the magnetoresistance component. The comparison between shunt resistor and magnetoresistance is experimentally performed. Finally, two inverter prototypes are presented, with one multi-level gate driver dedicated for GaN HEMT showing small switching loss performance.

Les semi-conducteurs à base de composés III-V de type GaN présentent de nombreux avantages – liés essentiellement à leur grande bande interdite - par rapport aux semi-conducteurs traditionnels Si, ou III-V des filières GaAs. De plus, il est possible de former, comme pour les semi-conducteurs traditionnels III-V des hétérojonctions de type HEMT (High Electron Mobility Transistor) AlGaN/GaN permettant d'obtenir à la fois une forte densité de porteurs confinés à l'hétérojonction et des mobilités électroniques élevées. Ces composants sont à l'heure actuelle les candidats les plus prometteurs pour des applications hyperfréquences de puissance. Cependant, l'échauffement observé au cours du fonctionnement et les différentes étapes de réalisation des composants ont un impact anormal sur les performances intrinsèques du composant. La microspectrométrie Raman est une technique nondestructive et sans contact avec une résolution spatiale submicronique, adaptée à l'étude des HEMTs AlGaN/GaN en fonctionnement. L'utilisation de différentes longueurs d'onde excitatrices visible et UV permet de sonder les hétérostructures à différentes profondeurs de pénétration. Les informations obtenues avec cette technique d'analyse sont la composition de l'hétérostructure, les contraintes entre les différentes couches, la résistance thermique aux interfaces, la qualité cristalline des différentes couches, le dopage et le comportement thermique des différentes couches. Le développement d'un système de microspectrométrie Raman UV résolue en temps a permis d'analyser le comportement thermique transitoire des HEMTs AlGaN/GaN en fonctionnement et plus particulièrement dans la zone active du composant.