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Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are becoming increasingly popular in power amplifier systems as an alternative to bulkier vacuum tube technologies. GaN offers advantages over other III-V semiconductor heterostructures such as a large bandgap energy, a low dielectric constant, and a high critical breakdown field. The aforementioned qualities make GaN a prime candidate for high-power and radiation-hardened applications using a smaller form-factor. Several different types of semiconductor substrates have been considered for their thermal properties and cost-effectiveness, and Silicon (Si) has been of increasing interest due to a balance between both factors. In this thesis, the DC, RF, and thermal characteristics of GaN HEMTs grown on Si-substrates will be investigated through a series of accelerated lifetime experiments. A figure of merit known as the critical voltage is explored and used as the primary means by which the GaN-on-Si devices are electrically strained. The critical voltage is defined as the specific voltage bias by which a sudden change in device performance is experienced due to a deformation of the target GaN HEMT’s epitaxial structure. Literature on the topic details the inevitable formation of pits and cracks localized under the drain-side of the gate contact that promote electrical degradation of the devices via the inverse piezoelectric effect. Characteristic changes in device performance due to high field strain are recorded and physical mechanisms behind observed degraded performance are investigated. The study assesses the performance of roughly 60 GaN-on-Si HEMTs in four experimental settings. The first experiment investigates the critical voltage of the device in the off-state mode of operation and explores device recovery post-stress. The second experiment analyzes alterations in DC and RF performance under varying thermal loads and tracks the dependence of the critical voltage on temperature. The third experiment examines electron trapping within the HEMTs as well as detrapping methodologies. The final experiment links the changes in RF performance induced by high field strain to the small-signal parameters of the HEMT. Findings from the research conclude the existence of process-dependent defects that originate during the growth process and lead to inherent electron traps in unstressed devices. Electron detrapping due to high electric field stress applied to the HEMTs was observed, potentially localized within the AlGaN layer or GaN buffer of the HEMT. The electron detrapping in turn contributed to drain current recovery and increased unilateral performance of the transistor in the RF regime. Thermal experiments resulted in a positive shift in critical voltage, which enhanced gate leakage current at lower gate voltage drives.

GaN-based HEMTs are among the most promising candidates for high-power and high-frequency applications; a niche for millimeter-wave technologies. Nitride materials indeed outperform other mainstream III-V materials (InP or GaAs) because of several properties, including wider bandgaps, high peak and saturation velocities, large breakdown voltages, together with good thermal conductivities. Nonetheless, the state-of-the-art of nitrides is not yet industrially mature to exploit the entire millimeter-wave range. A way to push further performance is to develop innovative designs, notably by exploring novel materials. The purpose of this research was therefore to investigate the use of boron-containing III-nitrides in high electron mobility transistors (HEMTs). The study was first conducted theoretically, through solving the Schrodinger-Poisson equation. Key parameters and relevant equations were derived to implement BGaN materials in our simulations. A GaN/ultrathin-BGaN/GaN heterojunction was showed to provide an electrostatic barrier to electrons and to improve the confinement of the two-dimensional electron gas. GaN back-barrier layers happen to limit leakage in the GaN buffer thanks to two effects: (i) a polarization-induced band discontinuity and (ii) a resistive barrier originating from excellent insulation properties of BGaN. The study was then, experimentally, several growth campaigns were carried out that led to the fabrication of devices. First, we confirmed the key characteristics of BGaN materials by electrical and optical measurements. Second, we demonstrated the evidence of a significant enhancement of performance of standard AlGaN/GaN structures by the introduction of a BGaN layer in the buffer layer. Compared to conventional AlGaN/GaN HEMTs, structures grown with BGaN back-barriers showed a significant improvement of static performances, transport properties, and trapping effects involving a limited current collapse in dynamic regime.

In this thesis, the investigation focuses on the analysis of the high frequency characteristics and the nonlinearity of the transistors. In view of the III-V semiconductors which have excellent high frequency performance and the advantage for high frequency circuit design, the 0.15£gm InGaAs based pseudomorphic high electron mobility transistors provided by WIN semiconductor Corp. were used in this study. The high frequency measurement was utilized to extract both extrinsic and intrinsic components of the transistors, and further to establish the small signal equivalent model in each bias condition. According to the physical definition of the extracted gm, gds and the relationship with the output current, RF I-V curves could be determined through the integration procedure. The nonlinearity of the transistors can be attributed to the nonlinear input capacitance Cgs and Cgd, and the voltage dependent current source. The high frequency nonlinear models proposed in this thesis were based on classic Angelov model. For the high frequency application, the frequency dependent characteristics of the nonlinear sources would be taken into consideration through the combination of the RF I-V curves and extracted intrinsic components. Thus, the nonlinearities could be able to describe by nonlinear function through the fitting process and model the output performance completely. The accuracy of the models could be confirmed through the comparison between the simulation and the measurement result. Obviously, the high frequency models which include the high frequency effect and the nonlinear characteristics have excellent agreement with the experimental data.

Cette thèse s’inscrit dans le cadre du développement d’une filière de transistors de puissance à base de nitrure de Gallium au CEA-LETI. Ces transistors, en particulier les HEMT utilisant l’hétérostructure AlGaN/GaN, présentent des propriétés très utiles pour les applications de puissance. L’essor de cette technologie passe notamment par le développement de contacts ohmiques peu résistifs. Cette thèse a pour objectif d’approfondir la compréhension des mécanismes de formation du contact ohmique sur une structure AlGaN/GaN. Dans un premier temps, une étude thermodynamique sur une dizaine de métaux de transition utilisables comme base de l’empilement métallique du contact a été menée, ce qui a permis de retenir une métallisation Ti/Al. Puis, les différentes réactions physico-chimiques de cet empilement avec des substrats nitrurés ont été étudiées en faisant varier la composition et les températures de recuit de formation du contact ohmique. Enfin, plusieurs études sur structure AlGaN/GaN couplant caractérisations électriques et physico-chimiques ont permis d’identifier des paramètres décisifs pour la réalisation d’un contact ohmique, peu résistif et nécessitant une faible température de recuit. / This PhD is part of the development of Gallium nitride based power transistors at the CEA-LETI. These transistors, especially those based on AlGaN/GaN heterostructure, are very promising for power electronics applications. The goal of this PhD is to increase the knowledge of the mechanisms responsible for the ohmic contact formation on a AlGaN/GaN structure. First, a thermodynamic study of several transition metals has been performed, leading us to select Ti/Al metallization. Then, the multiple physico-chemical reactions of this stack with nitride substrates have been studied depending on the stack composition and the annealing temperature. Finally, several studies on AlGaN/GaN structure coupling both physico-chemical and electrical characterizations reveal different decisive parameters for the formation of an ohmic contact with a low-resistance and a low annealing temperature.

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

Gallium Nitride (GaN) based transistors have been in the spotlight for power electronics due to promising properties like high bandgap, high breakdown field, high electron mobility, and high-frequency applications. While there are some commercial devices based on these transistors available, there is still room for improvement in these devices for widespread usage. In this project, GaN-based transistors fabricated at RISE AB were investigated. These devices had previously shown high leakage current. Different approaches taken to reduce the said leakage current were analysed. The main scope of the thesis was static electrical testing of a new batch of these transistors at room temperature, mainly investigating their leakage current. The new transistors were subjected to surface treatments and also a new in-situ dielectric layer was used. The surface treatments did not show much improvement but the in-situ grown dielectric showed almost half of the initial leakage current. In addition to this different device architectures with varying gate length, gate width, and gate to drain distance were tested and compared. It was found that devices with 3 μm gate length and 12 μm gate to drain distance showed the best performance. The blocking characteristic of the transistors was also tested and the devices could withstand up to 350V. Suggestions to further identify the sources of the leakage current are presented. Possible improvement in the design of the transistors to increase the blocking voltage is also described. / Transistorer baserade på galliumnitrid (GaN) har varit i strålkastaren för kraftelektronik på grund av lovande egenskaper som högt bandgap, högt nedbrytningsfält, hög elektronmobilitet. Dessa egenskaper gör materialet synnerligen lämpligt för komponentapplikationer vid höga effekter och, framför allt, höga frekvenser. Även om det finns några kommersiella applikationer baserade på dessa transistorer finns det fortfarande stort utrymme för förbättringar. I detta projekt undersöktes GaN-baserade transistorer tillverkade vid RISE AB. Dessa komponenter hade tidigare visat hög läckström och olika tillvägagångssätt för att minska nämnda läckström har analyserats. Transistorerna i detta projekt var ytbehandlade på ett nytt sätt och dielektirkat i styrelektroden var ocskå tillverkat på ett nytt sätt. Ytbehandlingarna visade inte mycket förbättring men det dielektrikat visade nästan hälften av den initiala läckströmmen. Utöver detta testades och jämfördes olika layouter med varierande geometri, gate-längd, gate-bredd och avstånd mellan gate/source. Det visade sig att komponenter med 3 μm gate-längd och 12 μm mellan gate och drain visade bästa prestanda. Transistorernas blockeringskaraktäristik testades också och visade sig tåla upp till 350V. Förslag för att ytterligare identifiera källorna till läckströmmen presenteras. Eventuell förbättring av utformningen av transistorerna för att öka blockeringsspänningen beskrivs också.

Gallium nitride (GaN) based high electron mobility transistors (HEMTs) are promising for power electronic applications due to their high breakdown voltage and power efficiency compared to Si-based power devices. As known, the design of the HEMT has high impact on the performance of the devices. In this project various GaN HEMTs on SiC substrate with different design configurations are characterized and investigated. These HEMTs are designed and fabricated by the Research Institutes of Sweden (RISE). The important properties of the HEMTs such as contact resistance, current density, capacitance, and breakdown voltage are characterized and emphasized. The uniformity of the contact resistance of the devices located across a 4’’ wafer is investigated, which reveals the lowest contact resistance of 4.3Ω·mm at the center of the wafer. The highest maximum current density of the devices is 1.15A/mm, and the maximum current scales with the gate dimensions of the devices. The gate capacitance of the devices is between 0.1 and 0.6pF under 1MHz. The gate insulation breakdown voltage of the devices is above 40V and the drain to source breakdown voltage is higher than 360V. Based on the results, discussions about the effects of the designs on the device performance are provided. Suggestions for further improvement of the device performance are given. / Galliumnitrid (GaN) baserade högelektronmobilitetstransistorer (HEMTs) är lovande för kraftelektroniska applikationer på grund av deras höga nedbrytningsspänning och effektivitet jämfört med Si-baserade kraftenheter. Som känt har designen av HEMT stor inverkan på enheternas prestanda. I detta projekt karakteriseras och undersöks olika GaN HEMTs på SiC-substrat med olika designkonfigurationer. Dessa HEMTs är designade och tillverkade av Sveriges forskningsins titut (RISE). De viktiga egenskaperna hos HEMTs såsom kontaktmotstånd, strömtäthet, kapacitans och nedbrytningsspänning karakteriseras och betonas. Enhetligheten i kontaktmotståndet för enheterna som är placerade över en 4'' skiva undersöks, vilket avslöjar det lägsta kontaktmotståndet på 4.3 Ω·mm i mitten av skivan. Den högsta maximala strömtätheten för enheterna är 1.15A/mm, och den maximala strömskalan med enheternas grindmått. Portens kapacitans för enheterna är mellan 0.1 och 0.6pF under 1MHz. Enhetsspänningen för grindisoleringen för enheterna är över 40V och avloppsspänningen till källan är högre än 360V. Baserat på resultaten ges diskussioner om designens effekter på enhetens prestanda. Förslag för ytterligare förbättring av enhetens prestanda ges.