Thesis (M.S.)--University of Wisconsin--Madison, 1969. / eContent provider-neutral record in process. Description based on print version record.

The thesis is concerned with techniques for realizing optimum control that are suited for analogue computers. The first half of the thesis develops an iterative scheme for the solution of the two point boundary value problem. The theory of the iterative scheme is covered in detail and the scheme is implemented on an analogue computer. Studies of the scheme have also been made using a digital computer. The iterative scheme can be modified to cope with constraints on the control law. These modifications have been tested on a digital computer. The latter half of the thesis is concerned with approximation techniques which produce, very simple controllers. These techniques require a large digital computer, such as the IBM 7040, to do the design calculations. The first approximation technique developed from the calculus of variations is covered in detail including a complete controller designed and simulated. The second approximation technique based on dynamic programming is discussed and a few points are made about the features of the controller. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.

No description available.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.

Pierre A. Humblet. / "January, 1983." Caption title. / Bibliography: leaves 9-10. / NSF Grant ECS 79-19880

This paper demonstrates conversion of an analog filter into a digital filter using computer aided software. The filter design to be demonstrated is a common third order Butterworth filter. This paper is not an attempt to review all filter designs or applications, but rather the attempt is to give a detailed explanation of the steps required to design almost any digital filter. No knowledge of the Intel Series 210 microcomputer development system is assumed. The appendices contain introduction to the Series 210 system. Chapter I demonstrates the steps needed to design this filter without computer aid. Included are both analog and digital filter response characteristics. Chapter II supplemented with Appendix C demonstrates the computer aided filter design. Again, filter characteristics are included. Chapter III compares the results of Chapter I and II. Even though this paper attempts to be inclusive of most of the computer details, it should not be used in exclusion of the available Series 210 manuals.

This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.